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Added support for MUL/DIV (Passes all tests)

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This commit is contained in:
felsabbagh3
2019-03-22 03:54:59 -04:00
parent 01d142c6e6
commit 097e0217de
12 changed files with 766 additions and 450 deletions
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6
rtl/VX_d_e_reg.v
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@@ -9,7 +9,7 @@ module VX_d_e_reg (
input wire[31:0] in_rd1, input wire[31:0] in_rd1,
input wire[4:0] in_rs2, input wire[4:0] in_rs2,
input wire[31:0] in_rd2, input wire[31:0] in_rd2,
input wire[3:0] in_alu_op, input wire[4:0] in_alu_op,
input wire[1:0] in_wb, input wire[1:0] in_wb,
input wire in_rs2_src, // NEW input wire in_rs2_src, // NEW
input wire[31:0] in_itype_immed, // new input wire[31:0] in_itype_immed, // new
@@ -37,7 +37,7 @@ module VX_d_e_reg (
output wire[31:0] out_rd1, output wire[31:0] out_rd1,
output wire[4:0] out_rs2, output wire[4:0] out_rs2,
output wire[31:0] out_rd2, output wire[31:0] out_rd2,
output wire[3:0] out_alu_op, output wire[4:0] out_alu_op,
output wire[1:0] out_wb, output wire[1:0] out_wb,
output wire out_rs2_src, // NEW output wire out_rs2_src, // NEW
output wire[31:0] out_itype_immed, // new output wire[31:0] out_itype_immed, // new
@@ -58,7 +58,7 @@ module VX_d_e_reg (
reg[31:0] rd1; reg[31:0] rd1;
reg[4:0] rs2; reg[4:0] rs2;
reg[31:0] rd2; reg[31:0] rd2;
reg[3:0] alu_op; reg[4:0] alu_op;
reg[1:0] wb; reg[1:0] wb;
reg[31:0] PC_next_out; reg[31:0] PC_next_out;
reg rs2_src; reg rs2_src;

25
rtl/VX_decode.v
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@@ -29,7 +29,7 @@ module VX_decode(
output wire[4:0] out_rs2, output wire[4:0] out_rs2,
output wire[31:0] out_rd2, output wire[31:0] out_rd2,
output wire[1:0] out_wb, output wire[1:0] out_wb,
output wire[3:0] out_alu_op, output wire[4:0] out_alu_op,
output wire out_rs2_src, // NEW output wire out_rs2_src, // NEW
output reg[31:0] out_itype_immed, // new output reg[31:0] out_itype_immed, // new
output wire[2:0] out_mem_read, // NEW output wire[2:0] out_mem_read, // NEW
@@ -45,7 +45,6 @@ module VX_decode(
wire[6:0] curr_opcode; wire[6:0] curr_opcode;
reg[3:0] alu_op;
wire[31:0] rd1_register; wire[31:0] rd1_register;
wire[31:0] rd2_register; wire[31:0] rd2_register;
@@ -94,8 +93,10 @@ module VX_decode(
wire[11:0] alu_shift_i_immed; wire[11:0] alu_shift_i_immed;
wire[1:0] csr_type; wire[1:0] csr_type;
reg[3:0] csr_alu;
reg[4:0] csr_alu;
reg[4:0] alu_op;
reg[4:0] mul_alu;
// always @(posedge clk) begin // always @(posedge clk) begin
// $display("Decode: curr_pc: %h", in_curr_PC); // $display("Decode: curr_pc: %h", in_curr_PC);
@@ -306,6 +307,20 @@ module VX_decode(
endcase endcase
end end
always @(*) begin
// ALU OP
case(func3)
3'h0: mul_alu = `MUL;
3'h1: mul_alu = `MULH;
3'h2: mul_alu = `MULHSU;
3'h3: mul_alu = `MULHU;
3'h4: mul_alu = `DIV;
3'h5: mul_alu = `DIVU;
3'h6: mul_alu = `REM;
3'h7: mul_alu = `REMU;
default: mul_alu = `NO_ALU;
endcase
end
assign csr_type = func3[1:0]; assign csr_type = func3[1:0];
@@ -318,14 +333,16 @@ module VX_decode(
endcase endcase
end end
wire[4:0] temp_final_alu;
assign out_alu_op = is_btype ? ((out_branch_type < `BLTU) ? `SUB : `SUBU) : assign temp_final_alu = is_btype ? ((out_branch_type < `BLTU) ? `SUB : `SUBU) :
is_lui ? `LUI_ALU : is_lui ? `LUI_ALU :
is_auipc ? `AUIPC_ALU : is_auipc ? `AUIPC_ALU :
is_csr ? csr_alu : is_csr ? csr_alu :
(is_stype || is_linst) ? `ADD : (is_stype || is_linst) ? `ADD :
alu_op; alu_op;
assign out_alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;
endmodule endmodule

42
rtl/VX_define.v
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@@ -46,23 +46,31 @@
`define BGTU 3'h6 `define BGTU 3'h6
`define NO_ALU 4'd15 `define NO_ALU 5'd15
`define ADD 4'd0 `define ADD 5'd0
`define SUB 4'd1 `define SUB 5'd1
`define SLLA 4'd2 `define SLLA 5'd2
`define SLT 4'd3 `define SLT 5'd3
`define SLTU 4'd4 `define SLTU 5'd4
`define XOR 4'd5 `define XOR 5'd5
`define SRL 4'd6 `define SRL 5'd6
`define SRA 4'd7 `define SRA 5'd7
`define OR 4'd8 `define OR 5'd8
`define AND 4'd9 `define AND 5'd9
`define SUBU 4'd10 `define SUBU 5'd10
`define LUI_ALU 4'd11 `define LUI_ALU 5'd11
`define AUIPC_ALU 4'd12 `define AUIPC_ALU 5'd12
`define CSR_ALU_RW 4'd13 `define CSR_ALU_RW 5'd13
`define CSR_ALU_RS 4'd14 `define CSR_ALU_RS 5'd14
`define CSR_ALU_RC 4'd15 `define CSR_ALU_RC 5'd15
`define MUL 5'd16
`define MULH 5'd17
`define MULHSU 5'd18
`define MULHU 5'd19
`define DIV 5'd20
`define DIVU 5'd21
`define REM 5'd22
`define REMU 5'd23

140
rtl/VX_execute.v
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@@ -7,7 +7,7 @@ module VX_execute (
input wire[31:0] in_rd1, input wire[31:0] in_rd1,
input wire[4:0] in_rs2, input wire[4:0] in_rs2,
input wire[31:0] in_rd2, input wire[31:0] in_rd2,
input wire[3:0] in_alu_op, input wire[4:0] in_alu_op,
input wire[1:0] in_wb, input wire[1:0] in_wb,
input wire in_rs2_src, // NEW input wire in_rs2_src, // NEW
input wire[31:0] in_itype_immed, // new input wire[31:0] in_itype_immed, // new
@@ -68,101 +68,53 @@ module VX_execute (
// $display("EXECUTE CURR_PC: %h",in_curr_PC); // $display("EXECUTE CURR_PC: %h",in_curr_PC);
// end // end
/* verilator lint_off UNUSED */
wire[63:0] mult_unsigned_result = ALU_in1 * ALU_in2;
wire[63:0] mult_signed_result = $signed(ALU_in1) * $signed(ALU_in2);
wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
wire[63:0] mult_signed_un_result = alu_in1_signed * ALU_in2;
/* verilator lint_on UNUSED */
always @(*) begin
case(in_alu_op)
`CSR_ALU_RW: out_csr_result = in_csr_mask;
`CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask;
`CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask);
default: out_csr_result = 32'hdeadbeef;
endcase
end
always @(*) begin always @(*) begin
case(in_alu_op) case(in_alu_op)
`ADD: `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
begin `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0];
out_csr_result = 32'hdeadbeef; `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
end `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
`SUB: `XOR: out_alu_result = ALU_in1 ^ ALU_in2;
begin `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0];
out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
// $display("PC: %h ----> %h and %h",in_curr_PC, $signed(ALU_in1), $signed(ALU_in2)); `OR: out_alu_result = ALU_in1 | ALU_in2;
out_csr_result = 32'hdeadbeef; `AND: out_alu_result = ALU_in2 & ALU_in1;
end `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
`SLLA: `LUI_ALU: out_alu_result = upper_immed;
begin `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
out_alu_result = ALU_in1 << ALU_in2[4:0]; `CSR_ALU_RW: out_alu_result = in_csr_data;
out_csr_result = 32'hdeadbeef; `CSR_ALU_RS: out_alu_result = in_csr_data;
end `CSR_ALU_RC: out_alu_result = in_csr_data;
`SLT: `MUL: out_alu_result = mult_signed_result[31:0];
begin `MULH: out_alu_result = mult_signed_result[63:32];
out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; `MULHSU: out_alu_result = mult_signed_un_result[63:32];
out_csr_result = 32'hdeadbeef; `MULHU: out_alu_result = mult_unsigned_result[63:32];
end `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : $signed($signed(ALU_in1) / $signed(ALU_in2));
`SLTU: `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : ALU_in1 / ALU_in2;
begin `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : $signed($signed(ALU_in1) % $signed(ALU_in2));
`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2;
out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; default: out_alu_result = 32'h0;
out_csr_result = 32'hdeadbeef;
end
`XOR:
begin
out_alu_result = ALU_in1 ^ ALU_in2;
out_csr_result = 32'hdeadbeef;
end
`SRL:
begin
out_alu_result = ALU_in1 >> ALU_in2[4:0];
out_csr_result = 32'hdeadbeef;
end
`SRA:
begin
out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
// $display("Shifting right arithmatic - PC: %h\t%h >>> %h = %h",in_curr_PC, $signed(ALU_in1), ALU_in2, out_alu_result);
out_csr_result = 32'hdeadbeef;
end
`OR:
begin
out_alu_result = ALU_in1 | ALU_in2;
out_csr_result = 32'hdeadbeef;
end
`AND:
begin
out_alu_result = ALU_in2 & ALU_in1;
out_csr_result = 32'hdeadbeef;
end
`SUBU:
begin
if (ALU_in1 >= ALU_in2) begin
out_alu_result = 32'h0;
end else begin
out_alu_result = 32'hffffffff;
end
out_csr_result = 32'hdeadbeef;
end
`LUI_ALU:
begin
out_alu_result = upper_immed;
out_csr_result = 32'hdeadbeef;
end
`AUIPC_ALU:
begin
out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
out_csr_result = 32'hdeadbeef;
end
`CSR_ALU_RW:
begin
out_alu_result = in_csr_data;
out_csr_result = in_csr_mask;
end
`CSR_ALU_RS:
begin
out_alu_result = in_csr_data;
out_csr_result = in_csr_data | in_csr_mask;
end
`CSR_ALU_RC:
begin
out_alu_result = in_csr_data;
out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask);
end
default:
begin
out_alu_result = 32'h0;
out_csr_result = 32'hdeadbeef;
end
endcase // in_alu_op endcase // in_alu_op
end end

BIN
rtl/obj_dir/Vvortex
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Binary file not shown.

586
rtl/obj_dir/Vvortex.cpp
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@@ -9,6 +9,8 @@
//-------------------- //--------------------
// STATIC VARIABLES // STATIC VARIABLES
// Begin mtask footprint all:
VL_ST_SIG8(VVortex::__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
//-------------------- //--------------------
@@ -183,9 +185,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type; = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type;
// ALWAYS at VX_e_m_reg.v:117 // ALWAYS at VX_e_m_reg.v:117
vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC;
// ALWAYS at VX_e_m_reg.v:117
vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset
= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed;
// ALWAYS at VX_d_e_reg.v:130 // ALWAYS at VX_d_e_reg.v:130
vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed
= (0xfffffU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) = (0xfffffU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -199,6 +198,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU) >> 0xcU)
: 0U)))); : 0U))));
// ALWAYS at VX_e_m_reg.v:117
vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset
= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed;
// ALWAYS at VX_d_e_reg.v:130 // ALWAYS at VX_d_e_reg.v:130
vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src =
(1U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) (1U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -353,19 +355,15 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr;
// ALWAYS at VX_e_m_reg.v:117 // ALWAYS at VX_e_m_reg.v:117
vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result
= ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) = ((0xdU == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? (vlTOPp->Vortex__DOT__csr_decode_csr_data
& ((IData)(0xffffffffU)
- vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask))
: (vlTOPp->Vortex__DOT__csr_decode_csr_data
| vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask))
: ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask
: 0xdeadbeefU)) : 0xdeadbeefU) : ((0xeU == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
: 0xdeadbeefU); ? (vlTOPp->Vortex__DOT__csr_decode_csr_data
| vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask)
: ((0xfU == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? (vlTOPp->Vortex__DOT__csr_decode_csr_data
& ((IData)(0xffffffffU) - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask))
: 0xdeadbeefU)));
// ALWAYS at VX_m_w_reg.v:60 // ALWAYS at VX_m_w_reg.v:60
vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd;
vlTOPp->out_cache_driver_in_data = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd2; vlTOPp->out_cache_driver_in_data = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd2;
@@ -453,87 +451,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
// ALWAYS at VX_d_e_reg.v:130 // ALWAYS at VX_d_e_reg.v:130
vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op =
((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
? 0xfU : ((0x63U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? 0xfU : (((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
? ((5U > (IData)(vlTOPp->Vortex__DOT__decode_branch_type)) >> 0x19U) & (0x33U == (0x7fU
? 1U : 0xaU) : ((0x37U ==
(0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0xbU :
((0x17U ==
(0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0xcU :
((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)
? ((1U
==
(3U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU)))
? 0xdU
: (
(2U
==
(3U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU)))
? 0xeU
: 0xfU))
: (((0x23U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
| (3U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))
? 0U ? (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu)
: ( : (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu)));
(0x4000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x2000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 9U
: 8U)
:
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0U
==
(0x7fU
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x19U)))
? 6U
: 7U)
: 5U))
:
((0x2000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 4U
: 3U)
:
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 2U
:
((0x13U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0U
:
((0U
==
(0x7fU
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x19U)))
? 0U
: 1U)))))))))));
// ALWAYS at VX_e_m_reg.v:117 // ALWAYS at VX_e_m_reg.v:117
vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd;
// ALWAYS at VX_m_w_reg.v:60 // ALWAYS at VX_m_w_reg.v:60
@@ -550,6 +472,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
// ALWAYS at VX_m_w_reg.v:60 // ALWAYS at VX_m_w_reg.v:60
vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb;
vlTOPp->Vortex__DOT__vx_execute__DOT__mult_signed_result
= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1),
VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2));
// ALWAYS at VX_d_e_reg.v:130 // ALWAYS at VX_d_e_reg.v:130
vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = ( vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = (
(~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) (~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling))
@@ -568,11 +493,81 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
// ALWAYS at VX_e_m_reg.v:117 // ALWAYS at VX_e_m_reg.v:117
vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb;
// ALWAYS at VX_execute.v:71 // ALWAYS at VX_execute.v:91
vlTOPp->Vortex__DOT__execute_alu_result = ((8U vlTOPp->Vortex__DOT__execute_alu_result = ((0x10U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ( ? (
(4U (8U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? 0U
:
((4U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((2U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((1U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((0U
== vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
:
VL_MODDIV_III(32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))
:
((0U
== vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
:
VL_MODDIVS_III(32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)))
:
((1U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((0U
== vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
? 0xffffffffU
:
VL_DIV_III(32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))
:
((0U
== vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
? 0xffffffffU
:
VL_DIVS_III(32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))
:
((2U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((1U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? (IData)(
(((QData)((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1))
* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)))
>> 0x20U))
: (IData)(
(((((QData)((IData)(
VL_NEGATE_I((IData)(
(1U
& (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
>> 0x1fU))))))
<< 0x20U)
| (QData)((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1)))
* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)))
>> 0x20U)))
:
((1U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? (IData)(
(vlTOPp->Vortex__DOT__vx_execute__DOT__mult_signed_result
>> 0x20U))
: (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__mult_signed_result)))))
: (
(8U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((4U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ?
((2U ((2U
@@ -610,8 +605,8 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
: :
(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
| vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)))) | vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))
: ( :
(4U ((4U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ?
((2U ((2U
@@ -662,7 +657,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
- vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
: :
(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
+ vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))); + vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))));
vlTOPp->out_cache_driver_in_address = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; vlTOPp->out_cache_driver_in_address = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result;
// ALWAYS at VX_memory.v:66 // ALWAYS at VX_memory.v:66
vlTOPp->Vortex__DOT__memory_branch_dir = (1U & vlTOPp->Vortex__DOT__memory_branch_dir = (1U &
@@ -839,16 +834,6 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype = vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype =
((0x13U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ((0x13U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
| (3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))); | (3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)));
vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr = (
(0x73U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
& (0U
!=
(7U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))));
vlTOPp->Vortex__DOT__decode_csr_address = (0xfffU vlTOPp->Vortex__DOT__decode_csr_address = (0xfffU
& (((0U & (((0U
!= !=
@@ -864,7 +849,33 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U) >> 0x14U)
: 0x55U)); : 0x55U));
// ALWAYS at VX_decode.v:259 // ALWAYS at VX_decode.v:310
vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU));
vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu =
vlTOPp->__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu
[vlTOPp->__Vtableidx1];
vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp
= (0xfffU & (((1U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))) | (5U
==
(7U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))))
? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) : (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)));
vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr = (
(0x73U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
& (0U
!=
(7U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))));
// ALWAYS at VX_decode.v:260
vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U
== ==
(0x7fU (0x7fU
@@ -895,16 +906,6 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
? 2U ? 2U
: 1U))) : 1U)))
: 0U); : 0U);
vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp
= (0xfffU & (((1U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))) | (5U
==
(7U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))))
? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) : (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)));
vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U
== (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))
? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle)
@@ -1010,7 +1011,7 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
>> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd))
& (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)));
// ALWAYS at VX_decode.v:248 // ALWAYS at VX_decode.v:249
vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? ( ? (
@@ -1145,6 +1146,87 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
>> 0x14U))) >> 0x14U)))
: 0xdeadbeefU) : 0xdeadbeefU)
: 0xdeadbeefU)))))); : 0xdeadbeefU))))));
vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu
= ((0x63U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? ((5U > (IData)(vlTOPp->Vortex__DOT__decode_branch_type))
? 1U : 0xaU) : ((0x37U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0xbU : ((0x17U ==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0xcU :
((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)
? ((1U
==
(3U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU)))
? 0xdU
:
((2U
==
(3U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU)))
? 0xeU
: 0xfU))
: (((0x23U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
| (3U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))
? 0U
:
((0x4000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x2000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 9U
: 8U)
:
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0U
==
(0x7fU
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x19U)))
? 6U
: 7U)
: 5U))
:
((0x2000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 4U
: 3U)
:
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 2U
:
((0x13U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0U
:
((0U
==
(0x7fU
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x19U)))
? 0U
: 1U))))))))));
// ALWAYS at VX_fetch.v:95 // ALWAYS at VX_fetch.v:95
vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = ( vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = (
((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal)
@@ -1155,11 +1237,98 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
& (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg)))
? vlTOPp->Vortex__DOT__memory_branch_dest ? vlTOPp->Vortex__DOT__memory_branch_dest
: vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use)); : vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use));
// ALWAYS at VX_execute.v:71 vlTOPp->Vortex__DOT__vx_execute__DOT__mult_signed_result
vlTOPp->Vortex__DOT__execute_alu_result = ((8U = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1),
VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2));
vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd
= (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd))
& (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)))) & (0U
!= (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)))
& (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)));
vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd
= (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd))
& (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)))
& (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)));
vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC;
// ALWAYS at VX_execute.v:91
vlTOPp->Vortex__DOT__execute_alu_result = ((0x10U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ( ? (
(4U (8U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? 0U
:
((4U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((2U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((1U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((0U
== vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
:
VL_MODDIV_III(32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))
:
((0U
== vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
:
VL_MODDIVS_III(32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)))
:
((1U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((0U
== vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
? 0xffffffffU
:
VL_DIV_III(32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))
:
((0U
== vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
? 0xffffffffU
:
VL_DIVS_III(32, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))
:
((2U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((1U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? (IData)(
(((QData)((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1))
* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)))
>> 0x20U))
: (IData)(
(((((QData)((IData)(
VL_NEGATE_I((IData)(
(1U
& (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
>> 0x1fU))))))
<< 0x20U)
| (QData)((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1)))
* (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)))
>> 0x20U)))
:
((1U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? (IData)(
(vlTOPp->Vortex__DOT__vx_execute__DOT__mult_signed_result
>> 0x20U))
: (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__mult_signed_result)))))
: (
(8U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
?
((4U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ?
((2U ((2U
@@ -1197,8 +1366,8 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
: :
(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
| vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)))) | vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))
: ( :
(4U ((4U
& (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
? ?
((2U ((2U
@@ -1249,21 +1418,7 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
- vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)
: :
(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1
+ vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))); + vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))));
vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd
= (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd))
& (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)))) & (0U
!= (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)))
& (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)));
vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd
= (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd))
& (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)))
& (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)));
vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC;
vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd
= ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))
@@ -1389,16 +1544,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype = vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype =
((0x13U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ((0x13U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
| (3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))); | (3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)));
vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr = (
(0x73U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
& (0U
!=
(7U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))));
vlTOPp->Vortex__DOT__decode_csr_address = (0xfffU vlTOPp->Vortex__DOT__decode_csr_address = (0xfffU
& (((0U & (((0U
!= !=
@@ -1414,7 +1559,33 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U) >> 0x14U)
: 0x55U)); : 0x55U));
// ALWAYS at VX_decode.v:259 // ALWAYS at VX_decode.v:310
vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU));
vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu =
vlTOPp->__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu
[vlTOPp->__Vtableidx1];
vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp
= (0xfffU & (((1U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))) | (5U
==
(7U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))))
? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) : (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)));
vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr = (
(0x73U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
& (0U
!=
(7U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))));
// ALWAYS at VX_decode.v:260
vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U
== ==
(0x7fU (0x7fU
@@ -1445,16 +1616,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
? 2U ? 2U
: 1U))) : 1U)))
: 0U); : 0U);
vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp
= (0xfffU & (((1U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))) | (5U
==
(7U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU))))
? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) : (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)));
vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd
= ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd))
@@ -1465,7 +1626,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
>> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd))
& (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)));
// ALWAYS at VX_decode.v:248 // ALWAYS at VX_decode.v:249
vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? ( ? (
@@ -1600,6 +1761,87 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
>> 0x14U))) >> 0x14U)))
: 0xdeadbeefU) : 0xdeadbeefU)
: 0xdeadbeefU)))))); : 0xdeadbeefU))))));
vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu
= ((0x63U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? ((5U > (IData)(vlTOPp->Vortex__DOT__decode_branch_type))
? 1U : 0xaU) : ((0x37U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0xbU : ((0x17U ==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0xcU :
((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)
? ((1U
==
(3U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU)))
? 0xdU
:
((2U
==
(3U
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0xcU)))
? 0xeU
: 0xfU))
: (((0x23U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
| (3U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))
? 0U
:
((0x4000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x2000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 9U
: 8U)
:
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0U
==
(0x7fU
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x19U)))
? 6U
: 7U)
: 5U))
:
((0x2000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
?
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 4U
: 3U)
:
((0x1000U
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
? 2U
:
((0x13U
==
(0x7fU
& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
? 0U
:
((0U
==
(0x7fU
& (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x19U)))
? 0U
: 1U))))))))));
vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd
= (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction
>> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd))
@@ -1806,13 +2048,15 @@ void VVortex::_ctor_var_reset() {
Vortex__DOT__vx_decode__DOT__is_itype = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__is_itype = VL_RAND_RESET_I(1);
Vortex__DOT__vx_decode__DOT__is_csr = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__is_csr = VL_RAND_RESET_I(1);
Vortex__DOT__vx_decode__DOT__alu_tempp = VL_RAND_RESET_I(12); Vortex__DOT__vx_decode__DOT__alu_tempp = VL_RAND_RESET_I(12);
Vortex__DOT__vx_decode__DOT__mul_alu = VL_RAND_RESET_I(5);
Vortex__DOT__vx_decode__DOT__temp_final_alu = VL_RAND_RESET_I(5);
{ int __Vi0=0; for (; __Vi0<32; ++__Vi0) { { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
}} }}
Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5); Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5);
Vortex__DOT__vx_d_e_reg__DOT__rd1 = VL_RAND_RESET_I(32); Vortex__DOT__vx_d_e_reg__DOT__rd1 = VL_RAND_RESET_I(32);
Vortex__DOT__vx_d_e_reg__DOT__rd2 = VL_RAND_RESET_I(32); Vortex__DOT__vx_d_e_reg__DOT__rd2 = VL_RAND_RESET_I(32);
Vortex__DOT__vx_d_e_reg__DOT__alu_op = VL_RAND_RESET_I(4); Vortex__DOT__vx_d_e_reg__DOT__alu_op = VL_RAND_RESET_I(5);
Vortex__DOT__vx_d_e_reg__DOT__wb = VL_RAND_RESET_I(2); Vortex__DOT__vx_d_e_reg__DOT__wb = VL_RAND_RESET_I(2);
Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = VL_RAND_RESET_I(32); Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = VL_RAND_RESET_I(32);
Vortex__DOT__vx_d_e_reg__DOT__rs2_src = VL_RAND_RESET_I(1); Vortex__DOT__vx_d_e_reg__DOT__rs2_src = VL_RAND_RESET_I(1);
@@ -1830,6 +2074,7 @@ void VVortex::_ctor_var_reset() {
Vortex__DOT__vx_d_e_reg__DOT__valid = VL_RAND_RESET_I(1); Vortex__DOT__vx_d_e_reg__DOT__valid = VL_RAND_RESET_I(1);
Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1); Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1);
Vortex__DOT__vx_execute__DOT__ALU_in2 = VL_RAND_RESET_I(32); Vortex__DOT__vx_execute__DOT__ALU_in2 = VL_RAND_RESET_I(32);
Vortex__DOT__vx_execute__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
Vortex__DOT__vx_e_m_reg__DOT__alu_result = VL_RAND_RESET_I(32); Vortex__DOT__vx_e_m_reg__DOT__alu_result = VL_RAND_RESET_I(32);
Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5); Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5);
Vortex__DOT__vx_e_m_reg__DOT__rd2 = VL_RAND_RESET_I(32); Vortex__DOT__vx_e_m_reg__DOT__rd2 = VL_RAND_RESET_I(32);
@@ -1864,4 +2109,13 @@ void VVortex::_ctor_var_reset() {
Vortex__DOT__vx_csr_handler__DOT__cycle = VL_RAND_RESET_Q(64); Vortex__DOT__vx_csr_handler__DOT__cycle = VL_RAND_RESET_Q(64);
Vortex__DOT__vx_csr_handler__DOT__instret = VL_RAND_RESET_Q(64); Vortex__DOT__vx_csr_handler__DOT__instret = VL_RAND_RESET_Q(64);
Vortex__DOT__vx_csr_handler__DOT__decode_csr_address = VL_RAND_RESET_I(12); Vortex__DOT__vx_csr_handler__DOT__decode_csr_address = VL_RAND_RESET_I(12);
__Vtableidx1 = VL_RAND_RESET_I(3);
__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[0] = 0x10U;
__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[1] = 0x11U;
__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[2] = 0x12U;
__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[3] = 0x13U;
__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[4] = 0x14U;
__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[5] = 0x15U;
__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[6] = 0x16U;
__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[7] = 0x17U;
} }

11
rtl/obj_dir/Vvortex.h
View File

@@ -48,8 +48,10 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid,0,0); VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,3,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rs2_src,0,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rs2_src,0,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_read,2,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_read,2,0);
@@ -98,10 +100,10 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register,31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd1,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd1,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd2,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd2,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
}; };
struct { struct {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
@@ -117,6 +119,7 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result,31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result,31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[32],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[32],31,0);
@@ -126,8 +129,10 @@ VL_MODULE(VVortex) {
// LOCAL VARIABLES // LOCAL VARIABLES
// Internals; generally not touched by application code // Internals; generally not touched by application code
// Begin mtask footprint all: // Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0); VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0); VL_SIG8(__Vclklast__TOP__reset,0,0);
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES // INTERNAL VARIABLES
// Internals; generally not touched by application code // Internals; generally not touched by application code

BIN
rtl/obj_dir/Vvortex__ALL.a
View File

Binary file not shown.

26
rtl/obj_dir/Vvortex__verFiles.dat
View File

@@ -2,11 +2,11 @@
C "-Wall -cc Vortex.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp" C "-Wall -cc Vortex.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v" S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 4626 12889079539 1553190875 0 1553190875 0 "VX_d_e_reg.v" S 4626 12889079539 1553237386 0 1553237386 0 "VX_d_e_reg.v"
S 8725 12889063385 1553236943 0 1553236943 0 "VX_decode.v" S 9200 12889063385 1553237914 0 1553237914 0 "VX_decode.v"
S 1351 12889079483 1553200040 0 1553200040 0 "VX_define.v" S 1503 12889079483 1553237629 0 1553237629 0 "VX_define.v"
S 3644 12889083963 1553196174 0 1553196174 0 "VX_e_m_reg.v" S 3644 12889083963 1553196174 0 1553196174 0 "VX_e_m_reg.v"
S 4919 12889081819 1553236958 0 1553236958 0 "VX_execute.v" S 4844 12889081819 1553241258 0 1553241258 0 "VX_execute.v"
S 1120 12889050060 1553236935 0 1553236935 0 "VX_f_d_reg.v" S 1120 12889050060 1553236935 0 1553236935 0 "VX_f_d_reg.v"
S 3537 12889047675 1553236929 0 1553236929 0 "VX_fetch.v" S 3537 12889047675 1553236929 0 1553236929 0 "VX_fetch.v"
S 5020 12889086478 1553236985 0 1553236985 0 "VX_forwarding.v" S 5020 12889086478 1553236985 0 1553236985 0 "VX_forwarding.v"
@@ -14,12 +14,12 @@ S 1578 12889085814 1553211072 0 1553211072 0 "VX_m_w_
S 2606 12889084513 1553234474 0 1553234474 0 "VX_memory.v" S 2606 12889084513 1553234474 0 1553234474 0 "VX_memory.v"
S 958 12889070228 1553234503 0 1553234503 0 "VX_register_file.v" S 958 12889070228 1553234503 0 1553234503 0 "VX_register_file.v"
S 806 12889086287 1553236964 0 1553236964 0 "VX_writeback.v" S 806 12889086287 1553236964 0 1553236964 0 "VX_writeback.v"
S 12863 12889050092 1553211358 0 1553211358 0 "Vortex.v" S 12863 12889050092 1553237368 0 1553237368 0 "Vortex.v"
T 78272 12889102709 1553237041 0 1553237041 0 "obj_dir/VVortex.cpp" T 88166 12889102709 1553241260 0 1553241260 0 "obj_dir/VVortex.cpp"
T 7758 12889102708 1553237041 0 1553237041 0 "obj_dir/VVortex.h" T 8044 12889102708 1553241260 0 1553241260 0 "obj_dir/VVortex.h"
T 1800 12889102711 1553237041 0 1553237041 0 "obj_dir/VVortex.mk" T 1800 12889102711 1553241260 0 1553241260 0 "obj_dir/VVortex.mk"
T 530 12889102707 1553237041 0 1553237041 0 "obj_dir/VVortex__Syms.cpp" T 530 12889102707 1553241260 0 1553241260 0 "obj_dir/VVortex__Syms.cpp"
T 711 12889102706 1553237041 0 1553237041 0 "obj_dir/VVortex__Syms.h" T 711 12889102706 1553241260 0 1553241260 0 "obj_dir/VVortex__Syms.h"
T 455 12889102712 1553237041 0 1553237041 0 "obj_dir/VVortex__ver.d" T 455 12889102712 1553241260 0 1553241260 0 "obj_dir/VVortex__ver.d"
T 0 0 1553237041 0 1553237041 0 "obj_dir/VVortex__verFiles.dat" T 0 0 1553241260 0 1553241260 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889102710 1553237041 0 1553237041 0 "obj_dir/VVortex_classes.mk" T 1159 12889102710 1553241260 0 1553241260 0 "obj_dir/VVortex_classes.mk"

72
rtl/results.txt
View File

@@ -340,3 +340,75 @@
# CPI: 1.04314 # CPI: 1.04314
# time to simulate: 6.95313e-310 milliseconds # time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING # GRADE: PASSING
**************** ../../src/riscv_tests/rv32um-p-div.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../src/riscv_tests/rv32um-p-divu.hex ****************
# Dynamic Instructions: 113
# of total cycles: 124
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09735
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../src/riscv_tests/rv32um-p-mul.hex ****************
# Dynamic Instructions: 589
# of total cycles: 600
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01868
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../src/riscv_tests/rv32um-p-mulh.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../src/riscv_tests/rv32um-p-mulhsu.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../src/riscv_tests/rv32um-p-mulhu.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../src/riscv_tests/rv32um-p-rem.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../src/riscv_tests/rv32um-p-remu.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING

10
rtl/test_bench.cpp
View File

@@ -2,7 +2,7 @@
#include "test_bench.h" #include "test_bench.h"
#define NUM_TESTS 38 #define NUM_TESTS 46
int main(int argc, char **argv) int main(int argc, char **argv)
{ {
@@ -52,6 +52,14 @@ int main(int argc, char **argv)
"../../src/riscv_tests/rv32ui-p-sw.hex", "../../src/riscv_tests/rv32ui-p-sw.hex",
"../../src/riscv_tests/rv32ui-p-xor.hex", "../../src/riscv_tests/rv32ui-p-xor.hex",
"../../src/riscv_tests/rv32ui-p-xori.hex", "../../src/riscv_tests/rv32ui-p-xori.hex",
"../../src/riscv_tests/rv32um-p-div.hex",
"../../src/riscv_tests/rv32um-p-divu.hex",
"../../src/riscv_tests/rv32um-p-mul.hex",
"../../src/riscv_tests/rv32um-p-mulh.hex",
"../../src/riscv_tests/rv32um-p-mulhsu.hex",
"../../src/riscv_tests/rv32um-p-mulhu.hex",
"../../src/riscv_tests/rv32um-p-rem.hex",
"../../src/riscv_tests/rv32um-p-remu.hex"
}; };
for (int ii = 0; ii < NUM_TESTS; ii++) for (int ii = 0; ii < NUM_TESTS; ii++)

4
rtl/vortex.v
View File

@@ -38,7 +38,7 @@ wire[31:0] decode_rd1;
wire[4:0] decode_rs2; wire[4:0] decode_rs2;
wire[31:0] decode_rd2; wire[31:0] decode_rd2;
wire[1:0] decode_wb; wire[1:0] decode_wb;
wire[3:0] decode_alu_op; wire[4:0] decode_alu_op;
wire decode_rs2_src; wire decode_rs2_src;
reg[31:0] decode_itype_immed; reg[31:0] decode_itype_immed;
wire[2:0] decode_mem_read; wire[2:0] decode_mem_read;
@@ -59,7 +59,7 @@ wire[4:0] d_e_rs1;
wire[31:0] d_e_rd1; wire[31:0] d_e_rd1;
wire[4:0] d_e_rs2; wire[4:0] d_e_rs2;
wire[31:0] d_e_rd2; wire[31:0] d_e_rd2;
wire[3:0] d_e_alu_op; wire[4:0] d_e_alu_op;
wire[1:0] d_e_wb; wire[1:0] d_e_wb;
wire d_e_rs2_src; wire d_e_rs2_src;
wire[31:0] d_e_itype_immed; wire[31:0] d_e_itype_immed;