wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

project tests refactoring

Browse Source
This commit is contained in:
Blaise Tine
2021-06-13 17:42:04 -07:00
parent 47c3234659
commit 03406c0a3f
631 changed files with 394471 additions and 653511 deletions
Download Patch File Download Diff File Expand all files Collapse all files
simX/Makefile
+1 -1
View File
@@ -25,7 +25,7 @@ all: $(PROJECT)
$(PROJECT): $(SRCS)
$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
run:
run-tests:
./test_rv32i.sh
./test_rv32f.sh
./test_runtime.sh
simX/test_runtime.sh
+8 -8
View File
@@ -3,12 +3,12 @@
set -e
make
make -C ../runtime/tests/dev
make -C ../runtime/tests/hello
make -C ../runtime/tests/nlTest
make -C ../runtime/tests/simple
make -C ../tests/runtime/dev
make -C ../tests/runtime/hello
make -C ../tests/runtime/nlTest
make -C ../tests/runtime/simple
./simX -a rv32i -i ../runtime/tests/dev/vx_dev_main.hex
./simX -a rv32i -i ../runtime/tests/hello/hello.hex
./simX -a rv32i -i ../runtime/tests/nlTest/vx_nl_main.hex
./simX -a rv32i -i ../runtime/tests/simple/vx_simple.hex
./simX -a rv32i -i ../tests/runtime/dev/vx_dev_main.hex
./simX -a rv32i -i ../tests/runtime/hello/hello.hex
./simX -a rv32i -i ../tests/runtime/nlTest/vx_nl_main.hex
./simX -a rv32i -i ../tests/runtime/simple/vx_simple.hex
simX/test_rv32f.sh
+22 -22
View File
@@ -4,35 +4,35 @@ set -e
make
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex
echo ../tests/riscv/isa/rv32uf-p-fadd.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fadd.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex
echo ../tests/riscv/isa/rv32uf-p-fmadd.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fmadd.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex
echo ../tests/riscv/isa/rv32uf-p-fmin.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fmin.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex
echo ../tests/riscv/isa/rv32uf-p-fcmp.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcmp.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fdst.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex
echo ../tests/riscv/isa/rv32uf-p-fdst.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-ldst.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex
echo ../tests/riscv/isa/rv32uf-p-fcvt.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcvt.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex
echo ../tests/riscv/isa/rv32uf-p-fcvt_w.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcvt_w.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-move.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-move.hex
echo ../tests/riscv/isa/rv32uf-p-move.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-move.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-recording.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex
echo ../tests/riscv/isa/rv32uf-p-recording.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-recoding.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex
echo ../tests/riscv/isa/rv32uf-p-fdiv.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fdiv.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex
echo ../tests/riscv/isa/rv32uf-p-fclass.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fclass.hex
simX/test_rv32i.sh
+92 -92
View File
@@ -4,140 +4,140 @@ set -e
make
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-add.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-add.hex
echo ./../tests/riscv/isa/rv32ui-p-add.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-add.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex
echo ./../tests/riscv/isa/rv32ui-p-addi.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-addi.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-and.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-and.hex
echo ./../tests/riscv/isa/rv32ui-p-and.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-and.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex
echo ./../tests/riscv/isa/rv32ui-p-andi.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-andi.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex
echo ./../tests/riscv/isa/rv32ui-p-auipc.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-auipc.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex
echo ./../tests/riscv/isa/rv32ui-p-beq.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-beq.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex
echo ./../tests/riscv/isa/rv32ui-p-bge.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bge.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex
echo ./../tests/riscv/isa/rv32ui-p-bgeu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bgeu.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex
echo ./../tests/riscv/isa/rv32ui-p-blt.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-blt.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex
echo ./../tests/riscv/isa/rv32ui-p-bltu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bltu.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex
echo ./../tests/riscv/isa/rv32ui-p-bne.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-bne.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex
echo ./../tests/riscv/isa/rv32ui-p-jal.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-jal.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex
echo ./../tests/riscv/isa/rv32ui-p-jalr.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-jalr.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex
echo ./../tests/riscv/isa/rv32ui-p-lb.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lb.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex
echo ./../tests/riscv/isa/rv32ui-p-lbu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lbu.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex
echo ./../tests/riscv/isa/rv32ui-p-lh.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lh.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex
echo ./../tests/riscv/isa/rv32ui-p-lhu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lhu.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex
echo ./../tests/riscv/isa/rv32ui-p-lui.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lui.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex
echo ./../tests/riscv/isa/rv32ui-p-lw.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-lw.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-or.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-or.hex
echo ./../tests/riscv/isa/rv32ui-p-or.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-or.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex
echo ./../tests/riscv/isa/rv32ui-p-ori.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-ori.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex
echo ./../tests/riscv/isa/rv32ui-p-sb.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sb.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex
echo ./../tests/riscv/isa/rv32ui-p-sh.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sh.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex
echo ./../tests/riscv/isa/rv32ui-p-simple.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-simple.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex
echo ./../tests/riscv/isa/rv32ui-p-sll.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sll.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex
echo ./../tests/riscv/isa/rv32ui-p-slli.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slli.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex
echo ./../tests/riscv/isa/rv32ui-p-slt.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slt.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex
echo ./../tests/riscv/isa/rv32ui-p-slti.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-slti.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex
echo ./../tests/riscv/isa/rv32ui-p-sltiu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sltiu.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex
echo ./../tests/riscv/isa/rv32ui-p-sltu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sltu.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex
echo ./../tests/riscv/isa/rv32ui-p-sra.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sra.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex
echo ./../tests/riscv/isa/rv32ui-p-srai.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srai.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex
echo ./../tests/riscv/isa/rv32ui-p-srl.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srl.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex
echo ./../tests/riscv/isa/rv32ui-p-srli.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-srli.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex
echo ./../tests/riscv/isa/rv32ui-p-sub.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sub.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex
echo ./../tests/riscv/isa/rv32ui-p-sw.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-sw.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex
echo ./../tests/riscv/isa/rv32ui-p-xor.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-xor.hex
echo ./../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex
echo ./../tests/riscv/isa/rv32ui-p-xori.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32ui-p-xori.hex
echo ./../benchmarks/riscv_tests/isa/rv32um-p-div.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32um-p-div.hex
echo ./../tests/riscv/isa/rv32um-p-div.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-div.hex
echo ./../benchmarks/riscv_tests/isa/rv32um-p-divu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32um-p-divu.hex
echo ./../tests/riscv/isa/rv32um-p-divu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-divu.hex
echo ./../benchmarks/riscv_tests/isa/rv32um-p-mul.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32um-p-mul.hex
echo ./../tests/riscv/isa/rv32um-p-mul.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mul.hex
echo ./../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex
echo ./../tests/riscv/isa/rv32um-p-mulh.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulh.hex
echo ./../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex
echo ./../tests/riscv/isa/rv32um-p-mulhsu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulhsu.hex
echo ./../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex
echo ./../tests/riscv/isa/rv32um-p-mulhu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-mulhu.hex
echo ./../benchmarks/riscv_tests/isa/rv32um-p-rem.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32um-p-rem.hex
echo ./../tests/riscv/isa/rv32um-p-rem.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-rem.hex
echo ./../benchmarks/riscv_tests/isa/rv32um-p-remu.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32um-p-remu.hex
echo ./../tests/riscv/isa/rv32um-p-remu.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32um-p-remu.hex