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CACHE WORKING just needs lb/sb

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This commit is contained in:
felsabbagh3
2019-10-25 03:03:09 -04:00
parent 1e648c5819
commit 01efe02e8b
19 changed files with 2302 additions and 2358 deletions
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17
rtl/cache/VX_cache_bank_valid.v vendored
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@@ -7,17 +7,16 @@ module VX_cache_bank_valid
(
input wire [`NT_M1:0] i_p_valid,
input wire [`NT_M1:0][31:0] i_p_addr,
output wire [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
output reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
);
genvar t_id;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
wire[2:0] threads_bank = i_p_addr[t_id][4:2];
assign thread_track_banks[threads_bank][t_id] = i_p_valid[t_id];
end
always @(*) begin
thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id];
end
end
endmodule