build warnings clean

2020-11-28 14:59:13 -05:00
parent 0c3d91ee6d
commit 00d7473268
16 changed files with 163 additions and 131 deletions
--- a/hw/rtl/VX_config.vh
+++ b/hw/rtl/VX_config.vh
@@ -202,16 +202,16 @@
 `define DCREQ_SIZE 4
 `endif

-// Miss Reserv Queue Knob
-`ifndef DMRVQ_SIZE
-`define DMRVQ_SIZE `MAX(`LSUQ_SIZE, 4)
-`endif
-
 // Core Writeback Queue Size
 `ifndef DCWBQ_SIZE
 `define DCWBQ_SIZE 4
 `endif

+// Miss Reserv Queue Knob
+`ifndef DMRVQ_SIZE
+`define DMRVQ_SIZE `MAX(`LSUQ_SIZE, 4)
+`endif
+
 // DRAM Request Queue Size
 `ifndef DDREQ_SIZE
 `define DDREQ_SIZE 4
@@ -244,16 +244,16 @@
 `define ICREQ_SIZE 4
 `endif

-// Miss Reserv Queue Knob
-`ifndef IMRVQ_SIZE
-`define IMRVQ_SIZE 4
-`endif
-
 // Core Writeback Queue Size
 `ifndef ICWBQ_SIZE
 `define ICWBQ_SIZE 4
 `endif

+// Miss Reserv Queue Knob
+`ifndef IMRVQ_SIZE
+`define IMRVQ_SIZE 4
+`endif
+
 // DRAM Request Queue Size
 `ifndef IDREQ_SIZE
 `define IDREQ_SIZE 4
@@ -303,16 +303,16 @@
 `define L2CREQ_SIZE 4
 `endif

-// Miss Reserv Queue Knob
-`ifndef L2MRVQ_SIZE
-`define L2MRVQ_SIZE 8
-`endif
-
 // Core Writeback Queue Size
 `ifndef L2CWBQ_SIZE
 `define L2CWBQ_SIZE 4
 `endif

+// Miss Reserv Queue Knob
+`ifndef L2MRVQ_SIZE
+`define L2MRVQ_SIZE 8
+`endif
+
 // DRAM Request Queue Size
 `ifndef L2DREQ_SIZE
 `define L2DREQ_SIZE 4
@@ -350,16 +350,16 @@
 `define L3CREQ_SIZE 4
 `endif

-// Miss Reserv Queue Knob
-`ifndef L3MRVQ_SIZE
-`define L3MRVQ_SIZE 8
-`endif
-
 // Core Writeback Queue Size
 `ifndef L3CWBQ_SIZE
 `define L3CWBQ_SIZE 4
 `endif

+// Miss Reserv Queue Knob
+`ifndef L3MRVQ_SIZE
+`define L3MRVQ_SIZE 8
+`endif
+
 // DRAM Request Queue Size
 `ifndef L3DREQ_SIZE
 `define L3DREQ_SIZE 4
--- a/hw/rtl/VX_lsu_unit.v
+++ b/hw/rtl/VX_lsu_unit.v
@@ -211,8 +211,8 @@ module VX_lsu_unit #(
   always @(posedge clk) begin
        if ((| dcache_req_if.valid) && dcache_req_if.ready) begin
            if (dcache_req_if.rw)
-                $display("%t: D$%0d Rw Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, rd=%0d, byteen=%0h, data=%0h", 
-                     $time, CORE_ID, req_wid, req_pc, dcache_req_if.valid, req_address, dcache_req_if.tag, req_rd, dcache_req_if.byteen, dcache_req_if.data);
+                $display("%t: D$%0d Rw Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, data=%0h", 
+                     $time, CORE_ID, req_wid, req_pc, dcache_req_if.valid, req_address, dcache_req_if.tag, dcache_req_if.byteen, dcache_req_if.data);
            else
                $display("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, rd=%0d, byteen=%0h", 
                     $time, CORE_ID, req_wid, req_pc, dcache_req_if.valid, req_address, dcache_req_if.tag, req_rd, dcache_req_if.byteen, dcache_req_if.data);
--- a/hw/simulate/Makefile
+++ b/hw/simulate/Makefile
@@ -1,8 +1,9 @@
-SINGLECORE += -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0
+CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors
+#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors

-#MULTICORE ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
-#MULTICORE ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
-MULTICORE ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
+CFLAGS += -Wno-aligned-new -Wno-maybe-uninitialized
+
+CFLAGS += -I../..

 # control RTL debug print states
 DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE  
@@ -21,66 +22,71 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
 DBG_FLAGS += $(DBG_PRINT_FLAGS)
 DBG_FLAGS += -DDBG_CACHE_REQ_INFO

-FPU_INCLUDE = -I../rtl/fp_cores -I../rtl/fp_cores/svdpi -I../rtl/fp_cores/fpnew/src/common_cells/include -I../rtl/fp_cores/fpnew/src/common_cells/src -I../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../rtl/fp_cores/fpnew/src 
-INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate $(FPU_INCLUDE)
+SINGLECORE += -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0
+
+#MULTICORE ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
+#MULTICORE ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
+MULTICORE ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
+
+TOP = Vortex
+
+RTL_DIR=../rtl
+
+FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/svdpi -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src 
+RTL_INCLUDE = -I$(RTL_DIR)/ -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE)

 SRCS = simulator.cpp testbench.cpp
-SRCS += ../rtl/fp_cores/svdpi/float_dpi.cpp
+SRCS += $(RTL_DIR)/fp_cores/svdpi/float_dpi.cpp

-all: build-s
+VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
+VL_FLAGS += -Wno-DECLFILENAME
+VL_FLAGS += --x-initial unique --x-assign unique
+VL_FLAGS += verilator.vlt

-CF += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors -I../..
-#CF += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors -I../..
+VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE)
+VL_FLAGS += --cc Vortex.v --top-module $(TOP)

-VF += -O2 --language 1800-2009 --assert -Wall -Wpedantic
-VF += -Wno-DECLFILENAME
-VF += --x-initial unique --x-assign unique
-VF += --exe $(SRCS) $(INCLUDE)
-VF += --cc Vortex.v --top-module Vortex
-VF += verilator.vlt
-
-DBG += -DVCD_OUTPUT $(DBG_FLAGS)
+DBG_FLAGS += -DVCD_OUTPUT $(DBG_FLAGS)

 THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

-OPT_FAST = "-Wno-aligned-new -Wmaybe-uninitialized" 
-OPT_SLOW = "-Wno-aligned-new -Wmaybe-uninitialized"
+all: build-s

 gen-s:
-	verilator $(VF) -DNDEBUG  $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)'
+	verilator $(VL_FLAGS) -DNDEBUG  $(SINGLECORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(SINGLECORE)'

 gen-sd:
-	verilator $(VF) $(SINGLECORE) -CFLAGS '$(CF) $(DBG) $(SINGLECORE)' --trace --trace-structs $(DBG)
+	verilator $(VL_FLAGS) $(SINGLECORE) -CFLAGS '$(CFLAGS) $(DBG_FLAGS) $(SINGLECORE)' --trace --trace-structs $(DBG_FLAGS)

 gen-st:
-	verilator $(VF) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)' --threads $(THREADS)
+	verilator $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(SINGLECORE)' --threads $(THREADS)

 gen-m:
-	verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
+	verilator $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(MULTICORE)'
 	
 gen-md:
-	verilator $(VF) $(MULTICORE) -CFLAGS '$(CF) $(DBG) $(MULTICORE)' --trace --trace-structs $(DBG)
+	verilator $(VL_FLAGS) $(MULTICORE) -CFLAGS '$(CFLAGS) $(DBG_FLAGS) $(MULTICORE)' --trace --trace-structs $(DBG_FLAGS)

 gen-mt:
-	verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' --threads $(THREADS)
+	verilator $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(MULTICORE)' --threads $(THREADS)

 build-s: gen-s
-	make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
+	make -j -C obj_dir -f VVortex.mk

 build-sd: gen-sd
-	make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
+	make -j -C obj_dir -f VVortex.mk

 build-st: gen-st
-	make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
+	make -j -C obj_dir -f VVortex.mk

 build-m: gen-m
-	make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
+	make -j -C obj_dir -f VVortex.mk

 build-md: gen-md
-	make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
+	make -j -C obj_dir -f VVortex.mk

 build-mt: gen-mt
-	make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
+	make -j -C obj_dir -f VVortex.mk

 run: run-s