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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-23 13:49:45 -04:00
parent 3cf1a5074b
commit 00a5122fd4
4 changed files with 138 additions and 145 deletions
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164
hw/rtl/VX_dmem_ctrl.v
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@@ -1,26 +1,26 @@
`include "VX_define.vh"
module VX_dmem_ctrl (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// Dram <-> Dcache
VX_cache_dram_req_if cache_dram_req_if,
VX_cache_dram_rsp_if cache_dram_rsp_if,
VX_cache_snp_req_rsp_if gpu_dcache_snp_req_if,
VX_cache_dram_req_if cache_dram_req_if,
VX_cache_dram_rsp_if cache_dram_rsp_if,
VX_cache_snp_req_if dcache_snp_req_if,
// Dram <-> Icache
VX_cache_dram_req_if gpu_icache_dram_req_if,
VX_cache_dram_rsp_if gpu_icache_dram_rsp_if,
VX_cache_snp_req_rsp_if gpu_icache_snp_req_if,
VX_cache_dram_req_if icache_dram_req_if,
VX_cache_dram_rsp_if icache_dram_rsp_if,
VX_cache_snp_req_if icache_snp_req_if,
// Core <-> Dcache
VX_cache_core_rsp_if dcache_rsp_if,
VX_cache_core_req_if dcache_req_if,
VX_cache_core_rsp_if dcache_core_rsp_if,
VX_cache_core_req_if dcache_core_req_if,
// Core <-> Icache
VX_cache_core_rsp_if icache_rsp_if,
VX_cache_core_req_if icache_req_if
VX_cache_core_rsp_if icache_core_rsp_if,
VX_cache_core_req_if icache_core_req_if
);
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_smem_if();
@@ -29,47 +29,47 @@ module VX_dmem_ctrl (
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_dcache_if();
VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_rsp_dcache_if();
wire to_shm = dcache_req_if.core_req_addr[0][31:24] == 8'hFF;
wire to_shm = dcache_core_req_if.core_req_addr[0][31:24] == 8'hFF;
wire dcache_wants_wb = (|dcache_rsp_dcache_if.core_rsp_valid);
// Dcache Request
assign dcache_req_dcache_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{~to_shm}};
assign dcache_req_dcache_if.core_req_read = dcache_req_if.core_req_read;
assign dcache_req_dcache_if.core_req_write = dcache_req_if.core_req_write;
assign dcache_req_dcache_if.core_req_addr = dcache_req_if.core_req_addr;
assign dcache_req_dcache_if.core_req_data = dcache_req_if.core_req_data;
assign dcache_req_dcache_if.core_req_rd = dcache_req_if.core_req_rd;
assign dcache_req_dcache_if.core_req_wb = dcache_req_if.core_req_wb;
assign dcache_req_dcache_if.core_req_warp_num = dcache_req_if.core_req_warp_num;
assign dcache_req_dcache_if.core_req_pc = dcache_req_if.core_req_pc;
assign dcache_req_dcache_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~to_shm}};
assign dcache_req_dcache_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_req_dcache_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_req_dcache_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_req_dcache_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_req_dcache_if.core_req_rd = dcache_core_req_if.core_req_rd;
assign dcache_req_dcache_if.core_req_wb = dcache_core_req_if.core_req_wb;
assign dcache_req_dcache_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num;
assign dcache_req_dcache_if.core_req_pc = dcache_core_req_if.core_req_pc;
assign dcache_rsp_dcache_if.core_rsp_ready = dcache_rsp_if.core_rsp_ready;
assign dcache_rsp_dcache_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready;
// Shared Memory Request
assign dcache_req_smem_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{to_shm}};
assign dcache_req_smem_if.core_req_addr = dcache_req_if.core_req_addr;
assign dcache_req_smem_if.core_req_data = dcache_req_if.core_req_data;
assign dcache_req_smem_if.core_req_read = dcache_req_if.core_req_read;
assign dcache_req_smem_if.core_req_write = dcache_req_if.core_req_write;
assign dcache_req_smem_if.core_req_rd = dcache_req_if.core_req_rd;
assign dcache_req_smem_if.core_req_wb = dcache_req_if.core_req_wb;
assign dcache_req_smem_if.core_req_warp_num = dcache_req_if.core_req_warp_num;
assign dcache_req_smem_if.core_req_pc = dcache_req_if.core_req_pc;
assign dcache_req_smem_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{to_shm}};
assign dcache_req_smem_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_req_smem_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_req_smem_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_req_smem_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_req_smem_if.core_req_rd = dcache_core_req_if.core_req_rd;
assign dcache_req_smem_if.core_req_wb = dcache_core_req_if.core_req_wb;
assign dcache_req_smem_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num;
assign dcache_req_smem_if.core_req_pc = dcache_core_req_if.core_req_pc;
assign dcache_rsp_smem_if.core_rsp_ready = dcache_rsp_if.core_rsp_ready && ~dcache_wants_wb;
assign dcache_rsp_smem_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready && ~dcache_wants_wb;
// Dcache Response
assign dcache_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid;
assign dcache_rsp_if.core_rsp_read = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_read : dcache_rsp_smem_if.core_rsp_read;
assign dcache_rsp_if.core_rsp_write = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_write : dcache_rsp_smem_if.core_rsp_write;
assign dcache_rsp_if.core_rsp_pc = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_pc : dcache_rsp_smem_if.core_rsp_pc;
assign dcache_rsp_if.core_rsp_data = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_data : dcache_rsp_smem_if.core_rsp_data;
assign dcache_rsp_if.core_rsp_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_warp_num : dcache_rsp_smem_if.core_rsp_warp_num;
assign dcache_core_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid;
assign dcache_core_rsp_if.core_rsp_read = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_read : dcache_rsp_smem_if.core_rsp_read;
assign dcache_core_rsp_if.core_rsp_write = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_write : dcache_rsp_smem_if.core_rsp_write;
assign dcache_core_rsp_if.core_rsp_pc = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_pc : dcache_rsp_smem_if.core_rsp_pc;
assign dcache_core_rsp_if.core_rsp_data = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_data : dcache_rsp_smem_if.core_rsp_data;
assign dcache_core_rsp_if.core_rsp_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_warp_num : dcache_rsp_smem_if.core_rsp_warp_num;
assign dcache_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready;
assign dcache_core_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready;
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_rsp_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) smem_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) smem_dram_rsp_if();
VX_cache #(
.CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES),
@@ -125,18 +125,18 @@ module VX_dmem_ctrl (
`IGNORE_WARNINGS_END
// DRAM response
.dram_rsp_valid (gpu_smem_dram_rsp_if.dram_rsp_valid),
.dram_rsp_addr (gpu_smem_dram_rsp_if.dram_rsp_addr),
.dram_rsp_data (gpu_smem_dram_rsp_if.dram_rsp_data),
.dram_rsp_valid (smem_dram_rsp_if.dram_rsp_valid),
.dram_rsp_addr (smem_dram_rsp_if.dram_rsp_addr),
.dram_rsp_data (smem_dram_rsp_if.dram_rsp_data),
// DRAM accept response
.dram_rsp_ready (gpu_smem_dram_req_if.dram_rsp_ready),
.dram_rsp_ready (smem_dram_req_if.dram_rsp_ready),
// DRAM Req
.dram_req_read (gpu_smem_dram_req_if.dram_req_read),
.dram_req_write (gpu_smem_dram_req_if.dram_req_write),
.dram_req_addr (gpu_smem_dram_req_if.dram_req_addr),
.dram_req_data (gpu_smem_dram_req_if.dram_req_data),
.dram_req_read (smem_dram_req_if.dram_req_read),
.dram_req_write (smem_dram_req_if.dram_req_write),
.dram_req_addr (smem_dram_req_if.dram_req_addr),
.dram_req_data (smem_dram_req_if.dram_req_data),
.dram_req_ready (0),
// Snoop Request
@@ -223,9 +223,9 @@ module VX_dmem_ctrl (
.dram_req_ready (cache_dram_req_if.dram_req_ready),
// Snoop Request
.snp_req_valid (gpu_dcache_snp_req_if.snp_req_valid),
.snp_req_addr (gpu_dcache_snp_req_if.snp_req_addr),
.snp_req_ready (gpu_dcache_snp_req_if.snp_req_ready),
.snp_req_valid (dcache_snp_req_if.snp_req_valid),
.snp_req_addr (dcache_snp_req_if.snp_req_addr),
.snp_req_ready (dcache_snp_req_if.snp_req_ready),
// Snoop Forward
`IGNORE_WARNINGS_BEGIN
@@ -261,52 +261,52 @@ module VX_dmem_ctrl (
.reset (reset),
// Core req
.core_req_valid (icache_req_if.core_req_valid),
.core_req_read (icache_req_if.core_req_read),
.core_req_write (icache_req_if.core_req_write),
.core_req_addr (icache_req_if.core_req_addr),
.core_req_data (icache_req_if.core_req_data),
.core_req_rd (icache_req_if.core_req_rd),
.core_req_wb (icache_req_if.core_req_wb),
.core_req_warp_num (icache_req_if.core_req_warp_num),
.core_req_pc (icache_req_if.core_req_pc),
.core_req_valid (icache_core_req_if.core_req_valid),
.core_req_read (icache_core_req_if.core_req_read),
.core_req_write (icache_core_req_if.core_req_write),
.core_req_addr (icache_core_req_if.core_req_addr),
.core_req_data (icache_core_req_if.core_req_data),
.core_req_rd (icache_core_req_if.core_req_rd),
.core_req_wb (icache_core_req_if.core_req_wb),
.core_req_warp_num (icache_core_req_if.core_req_warp_num),
.core_req_pc (icache_core_req_if.core_req_pc),
// Can submit core Req
.core_req_ready (icache_req_if.core_req_ready),
.core_req_ready (icache_core_req_if.core_req_ready),
// Core Cache Can't WB
.core_rsp_ready (icache_rsp_if.core_rsp_ready),
.core_rsp_ready (icache_core_rsp_if.core_rsp_ready),
// Cache CWB
.core_rsp_valid (icache_rsp_if.core_rsp_valid),
.core_rsp_read (icache_rsp_if.core_rsp_read),
.core_rsp_write (icache_rsp_if.core_rsp_write),
.core_rsp_warp_num (icache_rsp_if.core_rsp_warp_num),
.core_rsp_data (icache_rsp_if.core_rsp_data),
.core_rsp_pc (icache_rsp_if.core_rsp_pc),
.core_rsp_valid (icache_core_rsp_if.core_rsp_valid),
.core_rsp_read (icache_core_rsp_if.core_rsp_read),
.core_rsp_write (icache_core_rsp_if.core_rsp_write),
.core_rsp_warp_num (icache_core_rsp_if.core_rsp_warp_num),
.core_rsp_data (icache_core_rsp_if.core_rsp_data),
.core_rsp_pc (icache_core_rsp_if.core_rsp_pc),
`IGNORE_WARNINGS_BEGIN
.core_rsp_addr (),
`IGNORE_WARNINGS_END
// DRAM response
.dram_rsp_valid (gpu_icache_dram_rsp_if.dram_rsp_valid),
.dram_rsp_addr (gpu_icache_dram_rsp_if.dram_rsp_addr),
.dram_rsp_data (gpu_icache_dram_rsp_if.dram_rsp_data),
.dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid),
.dram_rsp_addr (icache_dram_rsp_if.dram_rsp_addr),
.dram_rsp_data (icache_dram_rsp_if.dram_rsp_data),
// DRAM accept response
.dram_rsp_ready (gpu_icache_dram_req_if.dram_rsp_ready),
.dram_rsp_ready (icache_dram_req_if.dram_rsp_ready),
// DRAM Req
.dram_req_read (gpu_icache_dram_req_if.dram_req_read),
.dram_req_write (gpu_icache_dram_req_if.dram_req_write),
.dram_req_addr (gpu_icache_dram_req_if.dram_req_addr),
.dram_req_data (gpu_icache_dram_req_if.dram_req_data),
.dram_req_ready (gpu_icache_dram_req_if.dram_req_ready),
.dram_req_read (icache_dram_req_if.dram_req_read),
.dram_req_write (icache_dram_req_if.dram_req_write),
.dram_req_addr (icache_dram_req_if.dram_req_addr),
.dram_req_data (icache_dram_req_if.dram_req_data),
.dram_req_ready (icache_dram_req_if.dram_req_ready),
// Snoop Request
.snp_req_valid (gpu_icache_snp_req_if.snp_req_valid),
.snp_req_addr (gpu_icache_snp_req_if.snp_req_addr),
.snp_req_ready (gpu_icache_snp_req_if.snp_req_ready),
.snp_req_valid (icache_snp_req_if.snp_req_valid),
.snp_req_addr (icache_snp_req_if.snp_req_addr),
.snp_req_ready (icache_snp_req_if.snp_req_ready),
// Snoop Forward
`IGNORE_WARNINGS_BEGIN