starting execution ... 
build model options ... 
argc=21
Generation context:
    HardFP is enabled enabling set to true 
    Faithful rounding constraint detected 
        Will not generate valid and channel signals 
    The new component name is acl_fdiv
    Frequency 250MHz 
    Deployment FPGA Arria10 
Estimated resources LUTs 539, DSPs 5, RAMBits 32768, RAMBlocks 3 
The pipeline depth of the block is 15 cycle(s)
@@start
@name FPDiv@
@latency 15@
@LUT 539@
@DSP 5@
@RAMBits 32768@
@RAMBlockUsage 3@
@enable 1@
@subnormals 0@
@error 1.00@
@rounding NA@
@method polynomial approximation@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ... 
build model options ... 
argc=20
Generation context:
    HardFP is enabled enabling set to true 
    Faithful rounding constraint detected 
        Will not generate valid and channel signals 
    The new component name is acl_fsqrt
    Frequency 250MHz 
    Deployment FPGA Arria10 
Estimated resources LUTs 271, DSPs 3, RAMBits 15872, RAMBlocks 3 
The pipeline depth of the block is 10 cycle(s)
@@start
@name FPSqrt@
@latency 10@
@LUT 271@
@DSP 3@
@RAMBits 15872@
@RAMBlockUsage 3@
@enable 1@
@subnormals 0@
@error 1.00@
@rounding NA@
@method polynomial approximation@
@inPort 0 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ... 
build model options ... 
argc=23
Generation context:
    HardFP is enabled enabling set to true 
    Faithful rounding constraint detected 
        Will not generate valid and channel signals 
    The new component name is acl_ftoi
    Frequency 250MHz 
    Deployment FPGA Arria10 
Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0 
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPToFXP@
@latency 3@
@LUT 327@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 1.00@
@rounding NA@
@method default@
@inPort 0 fpieee 8 23@
@outPort 0 fxp 32 0 1@
@nochanvalid 1@
@@end
starting execution ... 
build model options ... 
argc=23
Generation context:
    HardFP is enabled enabling set to true 
    Faithful rounding constraint detected 
        Will not generate valid and channel signals 
    The new component name is acl_ftou
    Frequency 250MHz 
    Deployment FPGA Arria10 
Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0 
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPToFXP@
@latency 3@
@LUT 287@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 1.00@
@rounding NA@
@method default@
@inPort 0 fpieee 8 23@
@outPort 0 fxp 32 0 0@
@nochanvalid 1@
@@end
starting execution ... 
build model options ... 
argc=23
Generation context:
    HardFP is enabled enabling set to true 
    Faithful rounding constraint detected 
        Will not generate valid and channel signals 
    The new component name is acl_itof
    Frequency 250MHz 
    Deployment FPGA Arria10 
Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0 
The pipeline depth of the block is 7 cycle(s)
@@start
@name FXPToFP@
@latency 7@
@LUT 397@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 1.00@
@rounding NA@
@method default@
@inPort 0 fxp 32 0 1@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ... 
build model options ... 
argc=23
Generation context:
    HardFP is enabled enabling set to true 
    Faithful rounding constraint detected 
        Will not generate valid and channel signals 
    The new component name is acl_utof
    Frequency 300MHz 
    Deployment FPGA Arria10 
Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0 
The pipeline depth of the block is 7 cycle(s)
@@start
@name FXPToFP@
@latency 7@
@LUT 363@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 1.00@
@rounding NA@
@method default@
@inPort 0 fxp 32 0 0@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
