72 lines
2.5 KiB
Scala
72 lines
2.5 KiB
Scala
//******************************************************************************
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// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
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// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
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//------------------------------------------------------------------------------
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package chipyard
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import chisel3._
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import chisel3.internal.sourceinfo.{SourceInfo}
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import freechips.rocketchip.prci._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
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import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.amba.axi4._
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import boom.common.{BoomTile}
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import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey}
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trait CanHaveHTIF { this: BaseSubsystem =>
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// Advertise HTIF if system can communicate with fesvr
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if (this match {
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case _: CanHavePeripherySerial if p(SerialKey) => true
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case _: HasPeripheryDebug if p(ExportDebug).dmi => true
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case _ => false
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}) {
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ResourceBinding {
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val htif = new Device {
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def describe(resources: ResourceBindings): Description = {
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val compat = resources("compat").map(_.value)
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Description("htif", Map(
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"compatible" -> compat))
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}
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}
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Resource(htif, "compat").bind(ResourceString("ucb,htif0"))
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}
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}
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}
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class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
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with HasTiles
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with CanHaveHTIF
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{
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def coreMonitorBundles = tiles.map {
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case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
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case b: BoomTile => b.module.core.coreMonitorBundle
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}.toList
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override lazy val module = new ChipyardSubsystemModuleImp(this)
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}
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class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
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with HasTilesModuleImp
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{
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// create file with core params
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ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
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// Generate C header with relevant information for Dromajo
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// This is included in the `dromajo_params.h` header file
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DromajoHelper.addArtefacts(InSubsystem)
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}
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