94 lines
3.8 KiB
Scala
94 lines
3.8 KiB
Scala
//******************************************************************************
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// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
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// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
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//------------------------------------------------------------------------------
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package chipyard
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import chisel3._
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import org.chipsalliance.cde.config.{Parameters, Field}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.{DontTouch}
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// ---------------------------------------------------------------------
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// Base system that uses the debug test module (dtm) to bringup the core
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// ---------------------------------------------------------------------
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/**
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* Base top with periphery devices and ports, and a BOOM + Rocket subsystem
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*/
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class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
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with HasAsyncExtInterrupts
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with CanHaveMasterTLMemPort // export TL port for outer memory
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with CanHaveMasterAXI4MemPort // expose AXI port for outer mem
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with CanHaveMasterAXI4MMIOPort
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with CanHaveSlaveAXI4Port
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{
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val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
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val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
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override lazy val module = new ChipyardSystemModule(this)
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}
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/**
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* Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
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*/
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class ChipyardSystemModule(_outer: ChipyardSystem) extends ChipyardSubsystemModuleImp(_outer)
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with HasRTCModuleImp
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with HasExtInterruptsModuleImp
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with DontTouch
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// ------------------------------------
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// TL Mem Port Mixin
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// ------------------------------------
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// Similar to ExtMem but instantiates a TL mem port
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case object ExtTLMem extends Field[Option[MemoryPortParams]](None)
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/** Adds a port to the system intended to master an TL DRAM controller. */
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trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
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require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty),
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"Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.")
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private val memPortParamsOpt = p(ExtTLMem)
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private val portName = "tl_mem"
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private val device = new MemoryDevice
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private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
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private val mbus = tlBusWrapperLocationMap.lift(MBUS).getOrElse(locateTLBusWrapper(SBUS))
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val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) =>
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Seq.tabulate(nMemoryChannels) { channel =>
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val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
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val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
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TLSlavePortParameters.v1(
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managers = Seq(TLSlaveParameters.v1(
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address = base.flatMap(_.intersect(filter)),
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resources = device.reg,
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regionType = RegionType.UNCACHED, // cacheable
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executable = true,
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supportsGet = TransferSizes(1, mbus.blockBytes),
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supportsPutFull = TransferSizes(1, mbus.blockBytes),
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supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
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beatBytes = memPortParams.beatBytes)
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}
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}).toList.flatten)
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// disable inwards monitors from node since the class with this trait (i.e. DigitalTop)
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// doesn't provide an implicit clock to those monitors
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mbus.coupleTo(s"memory_controller_port_named_$portName") {
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(DisableMonitors { implicit p => memTLNode :*= TLBuffer() }
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:*= TLSourceShrinker(1 << idBits)
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:*= TLWidthWidget(mbus.beatBytes)
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:*= _)
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}
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val mem_tl = InModuleBody { memTLNode.makeIOs() }
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}
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