46 lines
1.3 KiB
Scala
46 lines
1.3 KiB
Scala
package example
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import chisel3._
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import chisel3.experimental._
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import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
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import freechips.rocketchip.diplomacy.LazyModule
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.util.GeneratorApp
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// --------------------------
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// BOOM and/or Rocket Test Harness
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// --------------------------
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case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]]
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class BoomRocketTestHarness(implicit val p: Parameters) extends Module {
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val io = IO(new Bundle {
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val success = Output(Bool())
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})
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// force Chisel to rename module
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override def desiredName = "TestHarness"
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val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p)
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dut.debug := DontCare
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dut.connectSimAXIMem()
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dut.connectSimAXIMMIO()
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dut.dontTouchPorts()
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dut.tieOffInterrupts()
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dut.l2_frontend_bus_axi4.foreach(axi => {
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axi.tieoff()
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experimental.DataMirror.directionOf(axi.ar.ready) match {
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case core.ActualDirection.Input =>
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axi.r.bits := DontCare
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axi.b.bits := DontCare
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case core.ActualDirection.Output =>
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axi.aw.bits := DontCare
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axi.ar.bits := DontCare
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axi.w.bits := DontCare
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}
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})
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io.success := dut.connectSimSerial()
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}
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