[stevo]: adds a bunch of pad frame commits, as well as beginning work on clocking annotations and constraints * start add io pads pass * save progress adding yaml pad info * saving some semi-presentable work -- parses yaml for pad templates and associates templates with ports * added black boxes to the module; still need to hook up * added supply pad yaml example; added option to not include pad for an IO, blackboxed that cat + bit extraction functions * rewrite createbbs and some other parts of the transform * finally got blackboxhelper to work -- seems there was a typo in the firrtl pass (?) have not connected them up properly in the padframe * finished first version of pad transform; need to add bells and whistles + special case stuff * made a bunch of changes in firrtl to shorthand things * done with padframe for signals * started major refactoring; first of pad yaml stuff * forgot to update verilogTemplate -> verilog * rename ParsePadYaml -> ChipPadsYaml; moved some stuff * separated out stuff that describes pads i.e. direction, type, side * forgot to update import for yamlhelpers * trying to make the process of creating annotations more structured * saving annotation helpers but prob better to switch to yaml * saving changes -- reworking annotations * fixing some bugs; properly annotated ports with pads * annotate supply pads * lesson (re)learned. cleaned up constants * finished adding supply pads to pad frame; still need to generate io file * also committing updated transform; still without io file * big typo was causing pad verilog files not to be generated * verilator passes with transform; had to fix verilog bb typo * added unused pads; added more thorough tests + did visual inspection of output; made some port types more explicit * renamed files/classes to be clearer * started creating pad io template * update spec so that transform order matters * get rid of logger * went around in circles with blackboxhelper + way to annotate * finished adding + testing pad.io creation * starting clkgen pass -- made model for asynchronously reset clk divider + wrappers for programmatic bundling * temporarily locating albert's utility functions here * saving work on clk constraints * redid input config passing -- pass in tech directory instead; seems like getting clk sink, src, and relationship works * not done; need to pause to do tapeout-y things. the clk gen pass gets all the clks and their sources, but i need to build a proper graph to handle clks coming out of muxes
95 lines
3.8 KiB
Scala
95 lines
3.8 KiB
Scala
package barstools.tapeout.transforms.pads
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import net.jcazevedo.moultingyaml._
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import firrtl._
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import firrtl.ir._
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import barstools.tapeout.transforms._
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case class FoundryPad(
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tpe: String,
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name: String,
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width: Int,
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height: Int,
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supplySetNum: Option[Int],
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verilog: String) {
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def padInstName = "PAD"
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require(verilog.contains("{{#if isHorizontal}}"), "All pad templates must contain '{{#if isHorizontal}}'")
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require(verilog.contains("{{name}}"), "All pad templates must contain module name '{{name}}'")
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require(verilog.contains(padInstName), s"All pad templates should have instances called ${padInstName}")
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def getSupplySetNum = supplySetNum.getOrElse(1)
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val padType = tpe match {
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case "digital" =>
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require(verilog.contains(DigitalPad.inName), "Digital pad template must contain input called 'in'")
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require(verilog.contains(DigitalPad.outName), "Digital pad template must contain output called 'out'")
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require(verilog.contains("{{#if isInput}}"), "Digital pad template must contain '{{#if isInput}}'")
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DigitalPad
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case "analog" =>
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require(verilog.contains(AnalogPad.ioName), "Analog pad template must contain inout called 'io'")
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require(!verilog.contains("{{#if isInput}}"), "Analog pad template must not contain '{{#if isInput}}'")
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AnalogPad
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case "supply" =>
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// Supply pads don't have IO
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require(!verilog.contains("{{#if isInput}}"), "Supply pad template must not contain '{{#if isInput}}'")
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require(
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verilog.contains(s"${padInstName}["), "All supply pad templates should have instance arrays" +
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" called ${padInstName}[n:0], where n = ${getSupplySetNum-1}")
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require(supplySetNum.nonEmpty, "# of grouped supply pads 'supplySetNum' should be specified!")
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SupplyPad
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case _ => throw new Exception("Illegal pad type in config!")
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}
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import com.gilt.handlebars.scala.binding.dynamic._
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import com.gilt.handlebars.scala.Handlebars
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private val template = Handlebars(verilog)
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// Make sure names don't have spaces in Verilog!
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private[barstools] val correctedName = name.replace(" ", "_")
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case class TemplateParams(
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// isInput only used with digital pads
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isInput: Boolean,
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isHorizontal: Boolean) {
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private val orient = if (isHorizontal) Horizontal.serialize else Vertical.serialize
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private val dir = padType match {
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case AnalogPad => InOut.serialize
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case SupplyPad => NoDirection.serialize
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case DigitalPad => if (isInput) Input.serialize else Output.serialize
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}
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val name = {
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val start = Seq("pad", tpe, correctedName, orient)
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if (padType == DigitalPad) start :+ dir
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else start
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}.mkString("_")
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}
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// Note: Analog + supply don't use direction
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private def getTemplateParams(dir: Direction, orient: PadOrientation): TemplateParams =
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TemplateParams(isInput = (dir == Input), isHorizontal = (orient == Horizontal))
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def getVerilog(dir: Direction, orient: PadOrientation): String = {
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val p = getTemplateParams(dir, orient)
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template(p).stripMargin
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}
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def getName(dir: Direction, orient: PadOrientation): String = getTemplateParams(dir, orient).name
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}
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object FoundryPadsYaml extends DefaultYamlProtocol {
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val exampleResource = "/FoundryPads.yaml"
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implicit val _pad = yamlFormat6(FoundryPad)
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def parse(techDir: String): Seq[FoundryPad] = {
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val file = techDir + exampleResource
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if(techDir != "" && !(new java.io.File(file)).exists())
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throw new Exception("Technology directory must contain FoundryPads.yaml!")
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val out = (new YamlFileReader(exampleResource)).parse[FoundryPad](if (techDir == "") "" else file)
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val padNames = out.map(x => x.correctedName)
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require(padNames.distinct.length == padNames.length, "Pad names must be unique!")
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out
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}
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} |