abejgonzalez f1b40d51af Connected clocks | Exposed Master TL port

2020-09-15 12:58:58 -07:00

..

fpga-shells @ e8e7f8a321

First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.

2020-09-02 12:48:44 -07:00

src/main/scala

Connected clocks | Exposed Master TL port

2020-09-15 12:58:58 -07:00

.gitignore

Delete old makefiles | Full switch to CY make system

2020-09-03 21:28:05 -07:00

Makefile

Connected UART nicely

2020-09-11 16:55:25 -07:00