122 lines
3.3 KiB
Plaintext
122 lines
3.3 KiB
Plaintext
# Technology Setup
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# Technology used is ASAP7
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vlsi.core.technology: asap7
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# Specify dir with ASAP7 tarball
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technology.asap7.tarball_dir: ""
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vlsi.core.max_threads: 12
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# General Hammer Inputs
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# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
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vlsi.inputs.power_spec_mode: "auto"
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vlsi.inputs.power_spec_type: "cpf"
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# Specify clock signals
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vlsi.inputs.clocks: [
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{name: "clock", period: "1ns", uncertainty: "0.1ns"}
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]
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# Generate Make include to aid in flow
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vlsi.core.build_system: make
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# Power Straps
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par.power_straps_mode: generate
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par.generate_power_straps_method: by_tracks
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par.blockage_spacing: 2.0
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par.generate_power_straps_options:
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by_tracks:
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strap_layers:
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- M3
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- M4
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- M5
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- M6
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- M7
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- M8
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- M9
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pin_layers:
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- M9
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track_width: 7 # minimum allowed for M2 & M3
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track_spacing: 0
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track_spacing_M3: 1 # to avoid M2 shorts at higher density
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track_start: 10
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power_utilization: 0.2
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power_utilization_M8: 1.0
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power_utilization_M9: 1.0
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# Placement Constraints
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# For ASAP7, all numbers must be 4x larger than final GDS
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vlsi.inputs.placement_constraints:
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 800
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height: 500
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margins:
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left: 0
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right: 0
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top: 0
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bottom: 0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
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type: hardmacro
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x: 550
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y: 25
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orientation: "r0"
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top_layer: "M4"
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master: "SRAM1RW4096x8"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
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type: hardmacro
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x: 550
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y: 270
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orientation: "r0"
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top_layer: "M4"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
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type: hardmacro
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x: 675
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y: 25
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orientation: "r0"
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top_layer: "M4"
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master: "SRAM1RW4096x8"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
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type: hardmacro
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x: 675
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y: 270
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orientation: "r0"
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top_layer: "M4"
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master: "SRAM1RW4096x8"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
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type: hardmacro
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x: 125
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y: 150
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orientation: "my"
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top_layer: "M4"
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master: "SRAM1RW64x21"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 0
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y: 25
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orientation: "my"
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top_layer: "M4"
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master: "SRAM1RW1024x32"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
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type: hardmacro
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x: 0
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y: 260
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orientation: "my"
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top_layer: "M4"
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master: "SRAM1RW1024x37"
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# Pin placement constraints
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vlsi.inputs.pin_mode: generated
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vlsi.inputs.pin.generate_mode: semi_auto
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vlsi.inputs.pin.assignments: [
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{pins: "*", layers: ["M5", "M7"], side: "bottom"}
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]
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# SRAM Compiler compiler options
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vlsi.core.sram_generator_tool: "sram_compiler"
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# You should specify a location for the SRAM generator in the tech plugin
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vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/asap7"]
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vlsi.core.sram_generator_tool_path_meta: "append"
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