28 lines
784 B
Scala
28 lines
784 B
Scala
package example
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import chisel3._
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.config.{Field}
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import freechips.rocketchip.diplomacy.{LazyModule, AddressSet}
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import freechips.rocketchip.tilelink.{TLRAM}
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case class BackingScratchpadParams(
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base: BigInt,
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mask: BigInt)
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case object BackingScratchpadKey extends Field[Option[BackingScratchpadParams]](None)
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/**
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* Trait to add a scratchpad on the mbus
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*/
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trait CanHaveBackingScratchpad { this: BaseSubsystem =>
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private val portName = "Backing-Scratchpad"
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val spadOpt = p(BackingScratchpadKey).map { param =>
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val spad = LazyModule(new TLRAM(address=AddressSet(param.base, param.mask), beatBytes=mbus.beatBytes))
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mbus.toVariableWidthSlave(Some(portName)) { spad.node }
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spad
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}
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}
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