665 lines
29 KiB
Scala
665 lines
29 KiB
Scala
// See LICENSE for license details.
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/**
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* Terminology note:
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* mem - target memory to compile, in design (e.g. Mem() in rocket)
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* lib - technology SRAM(s) to use to compile mem
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*/
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package barstools.macros
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import firrtl._
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import firrtl.ir._
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import firrtl.PrimOps
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import firrtl.Utils._
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import firrtl.annotations._
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import firrtl.CompilerUtils.getLoweringTransforms
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import mdf.macrolib.{PolarizedPort, PortPolarity}
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import scala.collection.mutable.{ArrayBuffer, HashMap}
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import java.io.{File, FileWriter}
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import Utils._
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case class MacroCompilerException(msg: String) extends Exception(msg)
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/**
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* The MacroCompilerAnnotation to trigger the macro compiler.
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* Note that this annotation does NOT actually target any modules for
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* compilation. It simply holds all the settings for the memory compiler. The
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* actual selection of which memories to compile is set in the Params.
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*
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* To use, simply annotate the entire circuit itself with this annotation and
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* include [[MacroCompilerTransform]].
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*
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* TODO: make this into a "true" annotation?
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*/
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object MacroCompilerAnnotation {
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/** Macro compiler mode. */
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sealed trait CompilerMode
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/** Strict mode - must compile all memories or error out. */
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case object Strict extends CompilerMode
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/** Synflops mode - compile all memories with synflops (do not map to lib at all). */
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case object Synflops extends CompilerMode
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/** FallbackSynflops - compile all memories to SRAM when possible and fall back to synflops if a memory fails. **/
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case object FallbackSynflops extends CompilerMode
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/** CompileAvailable - compile what is possible and do nothing with uncompiled memories. **/
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case object CompileAvailable extends CompilerMode
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/**
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* The default mode for the macro compiler.
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* TODO: Maybe set the default to FallbackSynflops (typical for
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* vlsi_mem_gen-like scripts) once it's implemented?
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*/
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val Default = CompileAvailable
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/** Helper function to select a compiler mode. */
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def stringToCompilerMode(str: String): CompilerMode = (str: @unchecked) match {
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case "strict" => Strict
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case "synflops" => Synflops
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case "fallbacksynflops" => FallbackSynflops
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case "compileavailable" => CompileAvailable
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case "default" => Default
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case _ => throw new IllegalArgumentException("No such compiler mode " + str)
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}
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/**
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* Parameters associated to this MacroCompilerAnnotation.
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* @param mem Path to memory lib
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* @param lib Path to library lib or None if no libraries
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* @param costMetric Cost metric to use
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* @param mode Compiler mode (see CompilerMode)
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*/
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case class Params(mem: String, lib: Option[String], costMetric: CostMetric, mode: CompilerMode)
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/**
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* Create a MacroCompilerAnnotation.
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* @param c Top-level circuit name (see class description)
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* @param p Parameters (see above).
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*/
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def apply(c: String, p: Params): Annotation =
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Annotation(CircuitName(c), classOf[MacroCompilerTransform], MacroCompilerUtil.objToString(p))
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def unapply(a: Annotation) = a match {
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case Annotation(CircuitName(c), t, serialized) if t == classOf[MacroCompilerTransform] => {
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val p: Params = MacroCompilerUtil.objFromString(serialized).asInstanceOf[Params]
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Some(c, p)
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}
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case _ => None
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}
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}
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class MacroCompilerPass(mems: Option[Seq[Macro]],
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libs: Option[Seq[Macro]],
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costMetric: CostMetric = CostMetric.default,
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mode: MacroCompilerAnnotation.CompilerMode = MacroCompilerAnnotation.Default) extends firrtl.passes.Pass {
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def compile(mem: Macro, lib: Macro): Option[(Module, ExtModule)] = {
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val pairedPorts = mem.sortedPorts zip lib.sortedPorts
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// Width mapping
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/**
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* This is a list of submemories by width.
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* The tuples are (lsb, msb) inclusive.
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* e.g. (0, 7) and (8, 15) might be a split for a width=16 memory into two
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* width=8 memories.
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*/
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val bitPairs = ArrayBuffer[(BigInt, BigInt)]()
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var currentLSB = 0
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// Process every bit in the mem width.
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for (memBit <- 0 until mem.src.width) {
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val bitsInCurrentMem = memBit - currentLSB
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// Helper function to check if it's time to split memories.
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// @param effectiveLibWidth Split memory when we have this many bits.
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def splitMemory(effectiveLibWidth: Int): Unit = {
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if (bitsInCurrentMem == effectiveLibWidth) {
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bitPairs += ((currentLSB, memBit - 1))
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currentLSB = memBit
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}
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}
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for ((memPort, libPort) <- pairedPorts) {
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// Make sure we don't have a maskGran larger than the width of the memory.
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assert (memPort.src.effectiveMaskGran <= memPort.src.width)
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assert (libPort.src.effectiveMaskGran <= libPort.src.width)
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val libWidth = libPort.src.width
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// Don't consider cases of maskGran == width as "masked" since those masks
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// effectively function as write-enable bits.
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val memMask = if (memPort.src.effectiveMaskGran == memPort.src.width) None else memPort.src.maskGran
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val libMask = if (libPort.src.effectiveMaskGran == libPort.src.width) None else libPort.src.maskGran
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(memMask, libMask) match {
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// Neither lib nor mem is masked.
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// No problems here.
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case (None, None) => splitMemory(libWidth)
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// Only the lib is masked.
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// Not an issue; we can just make all the bits in the lib mask enabled.
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case (None, Some(p)) => splitMemory(libWidth)
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// Only the mem is masked.
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case (Some(p), None) => {
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if (p % libPort.src.width == 0) {
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// If the mem mask is a multiple of the lib width, then we're good.
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// Just roll over every lib width as usual.
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// e.g. lib width=4, mem maskGran={4, 8, 12, 16, ...}
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splitMemory(libWidth)
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} else if (libPort.src.width % p == 0) {
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// Lib width is a multiple of the mem mask.
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// Consider the case where mem mask = 4 but lib width = 8, unmasked.
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// We can still compile, but will need to waste the extra bits.
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splitMemory(memMask.get)
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} else {
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// No neat multiples.
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// We might still be able to compile extremely inefficiently.
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if (p < libPort.src.width) {
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// Compile using mem mask as the effective width. (note that lib is not masked)
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// e.g. mem mask = 3, lib width = 8
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splitMemory(memMask.get)
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} else {
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// e.g. mem mask = 13, lib width = 8
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System.err.println(s"Unmasked target memory: unaligned mem maskGran ${p} with lib (${lib.src.name}) width ${libPort.src.width} not supported")
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return None
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}
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}
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}
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// Both lib and mem are masked.
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case (Some(m), Some(l)) => {
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if (m == l) {
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// Lib maskGran == mem maskGran, no problems
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splitMemory(libWidth)
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} else if (m > l) {
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// Mem maskGran > lib maskGran
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if (m % l == 0) {
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// Mem maskGran is a multiple of lib maskGran, carry on as normal.
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splitMemory(libWidth)
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} else {
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System.err.println(s"Mem maskGran ${m} is not a multiple of lib maskGran ${l}: currently not supported")
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return None
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}
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} else { // m < l
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// Lib maskGran > mem maskGran.
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if (l % m == 0) {
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// Lib maskGran is a multiple of mem maskGran.
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// e.g. lib maskGran = 8, mem maskGran = 4.
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// In this case we can only compile very wastefully (by treating
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// lib as a mem maskGran width memory) :(
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splitMemory(memMask.get)
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// TODO: there's an optimization that could allow us to pack more
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// bits in and be more efficient.
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// e.g. say if mem maskGran = 4, lib maskGran = 8, libWidth = 32
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// We could use 16 of bit (bits 0-3, 8-11, 16-19, 24-27) instead
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// of treating it as simply a width 4 (!!!) memory.
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// This would require a major refactor though.
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} else {
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System.err.println(s"Lib maskGran ${m} is not a multiple of mem maskGran ${l}: currently not supported")
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return None
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}
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}
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}
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}
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}
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}
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// Add in the last chunk if there are any leftovers
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bitPairs += ((currentLSB, mem.src.width.toInt - 1))
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// Depth mapping
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val stmts = ArrayBuffer[Statement]()
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val outputs = HashMap[String, ArrayBuffer[(Expression, Expression)]]()
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val selects = HashMap[String, Expression]()
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val selectRegs = HashMap[String, Expression]()
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/* Palmer: If we've got a parallel memory then we've got to take the
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* address bits into account. */
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if (mem.src.depth > lib.src.depth) {
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mem.src.ports foreach { port =>
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val high = ceilLog2(mem.src.depth)
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val low = ceilLog2(lib.src.depth)
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val ref = WRef(port.address.name)
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val nodeName = s"${ref.name}_sel"
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val tpe = UIntType(IntWidth(high-low))
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selects(ref.name) = WRef(nodeName, tpe)
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stmts += DefNode(NoInfo, nodeName, bits(ref, high-1, low))
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// Donggyu: output selection should be piped
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if (port.output.isDefined) {
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val regName = s"${ref.name}_sel_reg"
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val enable = (port.chipEnable, port.readEnable) match {
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case (Some(ce), Some(re)) =>
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and(WRef(ce.name, BoolType), WRef(re.name, BoolType))
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case (Some(ce), None) => WRef(ce.name, BoolType)
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case (None, Some(re)) => WRef(re.name, BoolType)
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case (None, None) => one
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}
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selectRegs(ref.name) = WRef(regName, tpe)
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stmts += DefRegister(NoInfo, regName, tpe, WRef(port.clock.name), zero, WRef(regName))
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stmts += Connect(NoInfo, WRef(regName), Mux(enable, WRef(nodeName), WRef(regName), tpe))
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}
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}
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}
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for ((off, i) <- (0 until mem.src.depth by lib.src.depth).zipWithIndex) {
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for (j <- bitPairs.indices) {
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val name = s"mem_${i}_${j}"
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stmts += WDefInstance(NoInfo, name, lib.src.name, lib.tpe)
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// connect extra ports
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stmts ++= lib.extraPorts map { case (portName, portValue) =>
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Connect(NoInfo, WSubField(WRef(name), portName), portValue)
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}
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}
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for ((memPort, libPort) <- pairedPorts) {
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val addrMatch = selects get memPort.src.address.name match {
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case None => one
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case Some(addr) =>
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val index = UIntLiteral(i, IntWidth(bitWidth(addr.tpe)))
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DoPrim(PrimOps.Eq, Seq(addr, index), Nil, index.tpe)
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}
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val addrMatchReg = selectRegs get memPort.src.address.name match {
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case None => one
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case Some(reg) =>
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val index = UIntLiteral(i, IntWidth(bitWidth(reg.tpe)))
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DoPrim(PrimOps.Eq, Seq(reg, index), Nil, index.tpe)
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}
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def andAddrMatch(e: Expression) = {
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and(e, addrMatch)
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}
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val cats = ArrayBuffer[Expression]()
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for (((low, high), j) <- bitPairs.zipWithIndex) {
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val inst = WRef(s"mem_${i}_${j}", lib.tpe)
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def connectPorts2(mem: Expression,
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lib: String,
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polarity: Option[PortPolarity]): Statement =
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Connect(NoInfo, WSubField(inst, lib), portToExpression(mem, polarity))
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def connectPorts(mem: Expression,
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lib: String,
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polarity: PortPolarity): Statement =
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connectPorts2(mem, lib, Some(polarity))
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// Clock port mapping
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/* Palmer: FIXME: I don't handle memories with read/write clocks yet. */
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stmts += connectPorts(WRef(memPort.src.clock.name),
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libPort.src.clock.name,
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libPort.src.clock.polarity)
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// Adress port mapping
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/* Palmer: The address port to a memory is just the low-order bits of
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* the top address. */
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stmts += connectPorts(WRef(memPort.src.address.name),
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libPort.src.address.name,
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libPort.src.address.polarity)
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// Output port mapping
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(memPort.src.output, libPort.src.output) match {
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case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
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/* Palmer: In order to produce the output of a memory we need to cat
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* together a bunch of narrower memories, which can only be
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* done after generating all the memories. This saves up the
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* output statements for later. */
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val name = s"${mem}_${i}_${j}" // This name is the output from the instance (mem vs ${mem}).
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val exp = portToExpression(bits(WSubField(inst, lib), high-low, 0), Some(lib_polarity))
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stmts += DefNode(NoInfo, name, exp)
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cats += WRef(name)
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case (None, Some(lib)) =>
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/* Palmer: If the inner memory has an output port but the outer
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* one doesn't then it's safe to just leave the outer
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* port floating. */
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case (None, None) =>
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/* Palmer: If there's no output ports at all (ie, read-only
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* port on the memory) then just don't worry about it,
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* there's nothing to do. */
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case (Some(PolarizedPort(mem, _)), None) =>
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System.err println "WARNING: Unable to match output ports on memory"
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System.err println s" outer output port: ${mem}"
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return None
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}
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// Input port mapping
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(memPort.src.input, libPort.src.input) match {
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case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
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/* Palmer: The input port to a memory just needs to happen in parallel,
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* this does a part select to narrow the memory down. */
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stmts += connectPorts(bits(WRef(mem), high, low), lib, lib_polarity)
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case (None, Some(lib)) =>
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/* Palmer: If the inner memory has an input port but the other
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* one doesn't then it's safe to just leave the inner
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* port floating. This should be handled by the
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* default value of the write enable, so nothing should
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* every make it into the memory. */
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case (None, None) =>
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/* Palmer: If there's no input ports at all (ie, read-only
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* port on the memory) then just don't worry about it,
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* there's nothing to do. */
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case (Some(PolarizedPort(mem, _)), None) =>
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System.err println "WARNING: Unable to match input ports on memory"
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System.err println s" outer input port: ${mem}"
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return None
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}
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// Mask port mapping
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val memMask = memPort.src.maskPort match {
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case Some(PolarizedPort(mem, _)) =>
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/* Palmer: The bits from the outer memory's write mask that will be
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* used as the write mask for this inner memory. */
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if (libPort.src.effectiveMaskGran == libPort.src.width) {
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bits(WRef(mem), low / memPort.src.effectiveMaskGran)
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} else {
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require(isPowerOfTwo(libPort.src.effectiveMaskGran), "only powers of two masks supported for now")
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val effectiveLibWidth = if (memPort.src.maskGran.get < libPort.src.effectiveMaskGran) memPort.src.maskGran.get else libPort.src.width
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cat(((0 until libPort.src.width by libPort.src.effectiveMaskGran) map (i => {
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if (memPort.src.maskGran.get < libPort.src.effectiveMaskGran && i >= effectiveLibWidth) {
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// If the memMaskGran is smaller than the lib's gran, then
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// zero out the upper bits.
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zero
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} else {
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bits(WRef(mem), (low + i) / memPort.src.effectiveMaskGran)
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}
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})).reverse)
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}
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case None =>
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/* If there is a lib mask port but no mem mask port, just turn on
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* all bits of the lib mask port. */
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if (libPort.src.maskPort.isDefined) {
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val width = libPort.src.width / libPort.src.effectiveMaskGran
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val value = (BigInt(1) << width.toInt) - 1
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UIntLiteral(value, IntWidth(width))
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} else {
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// No mask ports on either side.
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// We treat a "mask" of a single bit to be equivalent to a write
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// enable (as used below).
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one
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}
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}
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// Write enable port mapping
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val memWriteEnable = memPort.src.writeEnable match {
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case Some(PolarizedPort(mem, _)) =>
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/* Palmer: The outer memory's write enable port, or a constant 1 if
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* there isn't a write enable port. */
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WRef(mem)
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case None =>
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/* Palmer: If there is no input port on the source memory port
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* then we don't ever want to turn on this write
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* enable. Otherwise, we just _always_ turn on the
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* write enable port on the inner memory. */
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if (memPort.src.input.isEmpty) zero else one
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}
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// Chip enable port mapping
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val memChipEnable = memPort.src.chipEnable match {
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case Some(PolarizedPort(mem, _)) => WRef(mem)
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case None => one
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}
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// Read enable port mapping
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/* Palmer: It's safe to ignore read enables, but we pass them through
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* to the vendor memory if there's a port on there that
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* implements the read enables. */
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(memPort.src.readEnable, libPort.src.readEnable) match {
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case (_, None) =>
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case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
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stmts += connectPorts(andAddrMatch(WRef(mem)), lib, lib_polarity)
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case (None, Some(PolarizedPort(lib, lib_polarity))) =>
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stmts += connectPorts(andAddrMatch(not(memWriteEnable)), lib, lib_polarity)
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}
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/* Palmer: This is actually the memory compiler: it figures out how to
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* implement the outer memory's collection of ports using what
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* the inner memory has availiable. */
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((libPort.src.maskPort, libPort.src.writeEnable, libPort.src.chipEnable): @unchecked) match {
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case (Some(PolarizedPort(mask, mask_polarity)), Some(PolarizedPort(we, we_polarity)), Some(PolarizedPort(en, en_polarity))) =>
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/* Palmer: This is the simple option: every port exists. */
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stmts += connectPorts(memMask, mask, mask_polarity)
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stmts += connectPorts(andAddrMatch(memWriteEnable), we, we_polarity)
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stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity)
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case (Some(PolarizedPort(mask, mask_polarity)), Some(PolarizedPort(we, we_polarity)), None) =>
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/* Palmer: If we don't have a chip enable but do have mask ports. */
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stmts += connectPorts(memMask, mask, mask_polarity)
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stmts += connectPorts(andAddrMatch(and(memWriteEnable, memChipEnable)),
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we, mask_polarity)
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case (None, Some(PolarizedPort(we, we_polarity)), chipEnable) =>
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if (bitWidth(memMask.tpe) == 1) {
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/* Palmer: If we're expected to provide mask ports without a
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* memory that actually has them then we can use the
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* write enable port instead of the mask port. */
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stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)),
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we, we_polarity)
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chipEnable match {
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case Some(PolarizedPort(en, en_polarity)) => {
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stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity)
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}
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case _ => // TODO: do we care about the case where mem has chipEnable but lib doesn't?
|
|
}
|
|
} else {
|
|
System.err.println("cannot emulate multi-bit mask ports with write enable")
|
|
return None
|
|
}
|
|
case (None, None, None) =>
|
|
// No write ports to match up (this may be a read-only port).
|
|
// This isn't necessarily an error condition.
|
|
}
|
|
}
|
|
// Cat macro outputs for selection
|
|
memPort.src.output match {
|
|
case Some(PolarizedPort(mem, _)) if cats.nonEmpty =>
|
|
val name = s"${mem}_${i}"
|
|
stmts += DefNode(NoInfo, name, cat(cats.toSeq.reverse))
|
|
(outputs getOrElseUpdate (mem, ArrayBuffer[(Expression, Expression)]())) +=
|
|
(addrMatchReg -> WRef(name))
|
|
case _ =>
|
|
}
|
|
}
|
|
}
|
|
// Connect mem outputs
|
|
mem.src.ports foreach { port =>
|
|
port.output match {
|
|
case Some(PolarizedPort(mem, _)) => outputs get mem match {
|
|
case Some(select) =>
|
|
val output = (select foldRight (zero: Expression)) {
|
|
case ((cond, tval), fval) => Mux(cond, tval, fval, fval.tpe) }
|
|
stmts += Connect(NoInfo, WRef(mem), output)
|
|
case None =>
|
|
}
|
|
case None =>
|
|
}
|
|
}
|
|
|
|
Some((mem.module(Block(stmts.toSeq)), lib.blackbox))
|
|
}
|
|
|
|
def run(c: Circuit): Circuit = {
|
|
val modules = (mems, libs) match {
|
|
case (Some(mems), Some(libs)) =>
|
|
// Try to compile each of the memories in mems.
|
|
// The 'state' is c.modules, which is a list of all the firrtl modules
|
|
// in the 'circuit'.
|
|
(mems foldLeft c.modules){ (modules, mem) =>
|
|
|
|
// Try to compile mem against each lib in libs, keeping track of the
|
|
// best compiled version, external lib used, and cost.
|
|
val (best, cost) = (libs foldLeft (None: Option[(Module, ExtModule)], BigInt(Long.MaxValue))){
|
|
case ((best, cost), lib) if mem.src.ports.size != lib.src.ports.size =>
|
|
/* Palmer: FIXME: This just assumes the Chisel and vendor ports are in the same
|
|
* order, but I'm starting with what actually gets generated. */
|
|
System.err println s"INFO: unable to compile ${mem.src.name} using ${lib.src.name} port count must match"
|
|
(best, cost)
|
|
case ((best, cost), lib) =>
|
|
// Run the cost function to evaluate this potential compile.
|
|
costMetric.cost(mem, lib) match {
|
|
case Some(newCost) => {
|
|
System.err.println(s"Cost of ${lib.src.name} for ${mem.src.name}: ${newCost}")
|
|
// Try compiling
|
|
compile(mem, lib) match {
|
|
// If it was successful and the new cost is lower
|
|
case Some(p) if (newCost < cost) => (Some(p), newCost)
|
|
case _ => (best, cost)
|
|
}
|
|
}
|
|
case _ => (best, cost) // Cost function rejected this combination.
|
|
}
|
|
}
|
|
|
|
// If we were able to compile anything, then replace the original module
|
|
// in the modules list with a compiled version, as well as the extmodule
|
|
// stub for the lib.
|
|
best match {
|
|
case None => {
|
|
if (mode == MacroCompilerAnnotation.Strict)
|
|
throw new MacroCompilerException(s"Target memory ${mem.src.name} could not be compiled and strict mode is activated - aborting.")
|
|
else
|
|
modules
|
|
}
|
|
case Some((mod, bb)) =>
|
|
(modules filterNot (m => m.name == mod.name || m.name == bb.name)) ++ Seq(mod, bb)
|
|
}
|
|
}
|
|
case _ => c.modules
|
|
}
|
|
c.copy(modules = modules)
|
|
}
|
|
}
|
|
|
|
class MacroCompilerTransform extends Transform {
|
|
def inputForm = MidForm
|
|
def outputForm = MidForm
|
|
def execute(state: CircuitState) = getMyAnnotations(state) match {
|
|
case Seq(MacroCompilerAnnotation(state.circuit.main, MacroCompilerAnnotation.Params(memFile, libFile, costMetric, mode))) =>
|
|
if (mode == MacroCompilerAnnotation.FallbackSynflops) {
|
|
throw new UnsupportedOperationException("Not implemented yet")
|
|
}
|
|
// Read, eliminate None, get only SRAM, make firrtl macro
|
|
val mems: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(Some(memFile)) match {
|
|
case Some(x:Seq[mdf.macrolib.Macro]) =>
|
|
Some(Utils.filterForSRAM(Some(x)) getOrElse(List()) map {new Macro(_)})
|
|
case _ => None
|
|
}
|
|
val libs: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(libFile) match {
|
|
case Some(x:Seq[mdf.macrolib.Macro]) =>
|
|
Some(Utils.filterForSRAM(Some(x)) getOrElse(List()) map {new Macro(_)})
|
|
case _ => None
|
|
}
|
|
val transforms = Seq(
|
|
new MacroCompilerPass(mems, libs, costMetric, mode),
|
|
new SynFlopsPass(mode == MacroCompilerAnnotation.Synflops, libs getOrElse mems.get))
|
|
(transforms foldLeft state)((s, xform) => xform runTransform s).copy(form=outputForm)
|
|
case _ => state
|
|
}
|
|
}
|
|
|
|
// FIXME: Use firrtl.LowerFirrtlOptimizations
|
|
class MacroCompilerOptimizations extends SeqTransform {
|
|
def inputForm = LowForm
|
|
def outputForm = LowForm
|
|
def transforms = Seq(
|
|
passes.RemoveValidIf,
|
|
new firrtl.transforms.ConstantPropagation,
|
|
passes.memlib.VerilogMemDelays,
|
|
new firrtl.transforms.ConstantPropagation,
|
|
passes.Legalize,
|
|
passes.SplitExpressions,
|
|
passes.CommonSubexpressionElimination)
|
|
}
|
|
|
|
class MacroCompiler extends Compiler {
|
|
def emitter = new VerilogEmitter
|
|
def transforms =
|
|
Seq(new MacroCompilerTransform) ++
|
|
getLoweringTransforms(firrtl.HighForm, firrtl.LowForm) ++
|
|
Seq(new MacroCompilerOptimizations)
|
|
}
|
|
|
|
object MacroCompiler extends App {
|
|
sealed trait MacroParam
|
|
case object Macros extends MacroParam
|
|
case object Library extends MacroParam
|
|
case object Verilog extends MacroParam
|
|
case object CostFunc extends MacroParam
|
|
case object Mode extends MacroParam
|
|
type MacroParamMap = Map[MacroParam, String]
|
|
type CostParamMap = Map[String, String]
|
|
val usage = Seq(
|
|
"Options:",
|
|
" -m, --macro-list: The set of macros to compile",
|
|
" -l, --library: The set of macros that have blackbox instances",
|
|
" -v, --verilog: Verilog output",
|
|
" -c, --cost-func: Cost function to use. Optional (default: \"default\")",
|
|
" -cp, --cost-param: Cost function parameter. (Optional depending on the cost function.). e.g. -c ExternalMetric -cp path /path/to/my/cost/script",
|
|
""" --mode:
|
|
| strict: Compile all memories to library or return an error.
|
|
| synflops: Produces synthesizable flop-based memories (for all memories and library memory macros); likely useful for simulation purposes.
|
|
| fallbacksynflops: Compile all memories to library when possible and fall back to synthesizable flop-based memories when library synth is not possible.
|
|
| compileavailable: Compile all memories to library when possible and do nothing in case of errors. (default)
|
|
""".stripMargin) mkString "\n"
|
|
|
|
def parseArgs(map: MacroParamMap, costMap: CostParamMap, args: List[String]): (MacroParamMap, CostParamMap) =
|
|
args match {
|
|
case Nil => (map, costMap)
|
|
case ("-m" | "--macro-list") :: value :: tail =>
|
|
parseArgs(map + (Macros -> value), costMap, tail)
|
|
case ("-l" | "--library") :: value :: tail =>
|
|
parseArgs(map + (Library -> value), costMap, tail)
|
|
case ("-v" | "--verilog") :: value :: tail =>
|
|
parseArgs(map + (Verilog -> value), costMap, tail)
|
|
case ("-c" | "--cost-func") :: value :: tail =>
|
|
parseArgs(map + (CostFunc -> value), costMap, tail)
|
|
case ("-cp" | "--cost-param") :: value1 :: value2 :: tail =>
|
|
parseArgs(map, costMap + (value1 -> value2), tail)
|
|
case "--mode" :: value :: tail =>
|
|
parseArgs(map + (Mode -> value), costMap, tail)
|
|
case arg :: tail =>
|
|
println(s"Unknown field $arg\n")
|
|
println(usage)
|
|
sys.exit(1)
|
|
}
|
|
|
|
def run(args: List[String]) {
|
|
val (params, costParams) = parseArgs(Map[MacroParam, String](), Map[String, String](), args)
|
|
try {
|
|
val macros = Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
|
|
|
|
// Open the writer for the output Verilog file.
|
|
val verilogWriter = new FileWriter(new File(params.get(Verilog).get))
|
|
|
|
if (macros.nonEmpty) {
|
|
// Note: the last macro in the input list is (seemingly arbitrarily)
|
|
// determined as the firrtl "top-level module".
|
|
val circuit = Circuit(NoInfo, macros, macros.last.name)
|
|
val annotations = AnnotationMap(
|
|
Seq(MacroCompilerAnnotation(
|
|
circuit.main,
|
|
MacroCompilerAnnotation.Params(
|
|
params.get(Macros).get, params.get(Library),
|
|
CostMetric.getCostMetric(params.getOrElse(CostFunc, "default"), costParams),
|
|
MacroCompilerAnnotation.stringToCompilerMode(params.getOrElse(Mode, "default"))
|
|
)
|
|
))
|
|
)
|
|
val state = CircuitState(circuit, HighForm, Some(annotations))
|
|
|
|
// Run the compiler.
|
|
val result = new MacroCompiler().compileAndEmit(state)
|
|
|
|
// Extract Verilog circuit and write it.
|
|
verilogWriter.write(result.getEmittedCircuit.value)
|
|
}
|
|
|
|
// Close the writer.
|
|
verilogWriter.close()
|
|
} catch {
|
|
case e: java.util.NoSuchElementException =>
|
|
println(usage)
|
|
sys.exit(1)
|
|
case e: MacroCompilerException =>
|
|
System.err.println(e.getMessage)
|
|
sys.exit(1)
|
|
case e: Throwable =>
|
|
throw e
|
|
}
|
|
}
|
|
|
|
run(args.toList)
|
|
}
|