e007b49179
* bump rocket-chip to enable large memory spaces * Tests pass with write mask bug fix * fix verisim build * Update to point to rocket-chip on master * bump rocket-chip and barstools This fixes the analog chisel bug and incorporates the firrtl MDF support (h/t John Wright)
84 lines
2.3 KiB
Makefile
84 lines
2.3 KiB
Makefile
base_dir=$(abspath ..)
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sim_dir=$(abspath .)
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PROJECT ?= example
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MODEL ?= TestHarness
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CONFIG ?= DefaultExampleConfig
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CFG_PROJECT ?= $(PROJECT)
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TB ?= TestDriver
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TOP ?= ExampleTop
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sim_name = vcs
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simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
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simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
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default: $(simv)
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debug: $(simv_debug)
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include $(base_dir)/Makefrag
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ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
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-include $(build_dir)/$(long_name).d
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endif
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rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
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sim_vsrcs = \
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$(VERILOG_FILE) \
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$(HARNESS_FILE) \
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$(HARNESS_SMEMS_FILE) \
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$(SMEMS_FILE)
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VCS = vcs -full64
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -f $(sim_dotf) \
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$(RISCV)/lib/libfesvr.so \
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-sverilog \
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+incdir+$(generated_dir) \
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+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+STOP_COND=!$(TB).reset \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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+libext+.v \
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verilog: $(sim_vsrcs)
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$(simv): $(sim_vsrcs) $(sim_dotf)
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rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
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-debug_pp
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$(simv_debug) : $(sim_vsrcs) $(sim_dotf)
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rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
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+define+DEBUG -debug_pp
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$(output_dir)/%.out: $(output_dir)/% $(simv)
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$(simv) +permissive -q +ntb_random_seed_automatic +verbose +max-cycles=1000000 +permissive-off $< 3>&1 1>&2 2>&3 | spike-dasm > $@
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$(output_dir)/%.run: $(output_dir)/% $(simv)
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$(simv) +permissive -q +ntb_random_seed_automatic +max-cycles=1000000 +permissive-off $< && touch $@
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$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
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$(simv_debug) +permissive -q +ntb_random_seed_automatic +vcdplusfile=$@ +max-cycles=1000000 +permissive-off $<
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run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
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run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
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run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
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clean:
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rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h
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.PHONY: clean
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