73 lines
2.8 KiB
Scala
73 lines
2.8 KiB
Scala
//// See LICENSE for license details.
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//package chipyard.fpga.arty.e300
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//
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//import freechips.rocketchip.config._
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//import freechips.rocketchip.subsystem._
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//import freechips.rocketchip.devices.debug._
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//import freechips.rocketchip.devices.tilelink._
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//import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
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//import freechips.rocketchip.system._
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//import freechips.rocketchip.tile._
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//
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//import sifive.blocks.devices.mockaon._
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//import sifive.blocks.devices.gpio._
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//import sifive.blocks.devices.pwm._
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//import sifive.blocks.devices.spi._
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//import sifive.blocks.devices.uart._
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//import sifive.blocks.devices.i2c._
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//
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//import chipyard.{BuildSystem}
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//
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//class E300DevKitExtra extends Config((site, here, up) => {
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// case PeripheryGPIOKey => List(
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// GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
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// case PeripheryPWMKey => List(
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// PWMParams(address = 0x10015000, cmpWidth = 8),
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// PWMParams(address = 0x10025000, cmpWidth = 16),
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// PWMParams(address = 0x10035000, cmpWidth = 16))
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// case PeripherySPIKey => List(
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// SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3),
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// SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3))
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// case PeripherySPIFlashKey => List(
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// SPIFlashParams(
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// fAddress = 0x20000000,
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// rAddress = 0x10014000,
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// defaultSampleDel = 3))
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// case PeripheryUARTKey => List(
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// UARTParams(address = 0x10013000),
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// UARTParams(address = 0x10023000))
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// case PeripheryI2CKey => List(
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// I2CParams(address = 0x10016000))
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// case PeripheryMockAONKey =>
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// MockAONParams(address = 0x10000000)
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// case DTSTimebase => BigInt(32768)
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// case JtagDTMKey => new JtagDTMConfig (
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// idcodeVersion = 2,
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// idcodePartNum = 0x000,
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// idcodeManufId = 0x489,
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// debugIdleCycles = 5)
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//})
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//
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//class WithE300System extends Config((site, here, up) => {
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// case BuildSystem => (p: Parameters) => new E300DigitalTop()(p)
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//})
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//
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//class E300ArtyDevKitConfig extends Config(
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// new WithE300System ++
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// new WithE300Connections ++
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// new E300DevKitExtra ++
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// new chipyard.config.WithBootROM ++
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// new chipyard.config.WithL2TLBs(1024) ++
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// new freechips.rocketchip.subsystem.With1TinyCore ++
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// new freechips.rocketchip.subsystem.WithNBanks(0) ++
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// new freechips.rocketchip.subsystem.WithNoMemPort ++
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// new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
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// new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
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// new freechips.rocketchip.subsystem.WithJtagDTM ++
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// new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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// new freechips.rocketchip.subsystem.WithNoSlavePort ++
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// new freechips.rocketchip.subsystem.WithInclusiveCache ++
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// new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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// new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
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// new freechips.rocketchip.system.BaseConfig)
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