142 lines
5.4 KiB
Scala
142 lines
5.4 KiB
Scala
package chipyard.fpga.vc707
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import chisel3._
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import chisel3.experimental.{IO}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
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import org.chipsalliance.cde.config.{Parameters}
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import freechips.rocketchip.tilelink.{TLClientNode}
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import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
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import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
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import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
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import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, LEDOverlayKey, LEDDesignInput, SwitchOverlayKey, SwitchDesignInput, ButtonOverlayKey, ButtonDesignInput, SPIOverlayKey, SPIDesignInput, ChipLinkOverlayKey, ChipLinkDesignInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, JTAGDebugOverlayKey, JTAGDebugDesignInput}
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import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
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import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
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import chipyard.{ChipTop, ExtTLMem, CanHaveMasterTLMemPort}
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import chipyard.iobinders.{HasIOBinders}
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import chipyard.harness.{ApplyHarnessBinders, HasHarnessSignalReferences, BuildTop, DefaultClockFrequencyKey}
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class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>
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def dp = designParameters
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// Order matters; ddr depends on sys_clock
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val uart = Overlay(UARTOverlayKey, new UARTVC707ShellPlacer(this, UARTShellInput()))
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val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
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// place all clocks in the shell
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require(dp(ClockInputOverlayKey).size >= 1)
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val sysClkNode = dp(ClockInputOverlayKey).head.place(ClockInputDesignInput()).overlayOutput.node
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/*** Connect/Generate clocks ***/
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// connect to the PLL that will generate multiple clocks
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val harnessSysPLL = dp(PLLFactoryKey)()
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harnessSysPLL := sysClkNode
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// create and connect to the dutClock
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println(s"VC707 FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
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val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
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val dutWrangler = LazyModule(new ResetWrangler)
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val dutGroup = ClockGroup()
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dutClock := dutWrangler.node := dutGroup := harnessSysPLL
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/*** LED ***/
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val ledModule = dp(LEDOverlayKey).map(_.place(LEDDesignInput()).overlayOutput.led)
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/*** Switch ***/
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val switchModule = dp(SwitchOverlayKey).map(_.place(SwitchDesignInput()).overlayOutput.sw)
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/*** Button ***/
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val buttonModule = dp(ButtonOverlayKey).map(_.place(ButtonDesignInput()).overlayOutput.but)
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/*** JTAG ***/
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val jtagModule = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput()).overlayOutput.jtag
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/*** UART ***/
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// 1st UART goes to the VC707 dedicated UART
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val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head)))
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dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
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/*** SPI ***/
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// 1st SPI goes to the VC707 SDIO port
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val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head)))
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dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb))
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/*** DDR ***/
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// Modify the last field of `DDRDesignInput` for 1GB RAM size
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val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL, true)).overlayOutput.ddr
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// connect 1 mem. channel to the FPGA DDR
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val inParams = topDesign match { case td: ChipTop =>
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td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
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lsys.memTLNode.edges.in(0)
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}
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}
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val ddrClient = TLClientNode(Seq(inParams.master))
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ddrNode := ddrClient
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// module implementation
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override lazy val module = new VC707FPGATestHarnessImp(this)
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}
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class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
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val vc707Outer = _outer
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val reset = IO(Input(Bool()))
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_outer.xdc.addBoardPin(reset, "reset")
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val resetIBUF = Module(new IBUF)
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resetIBUF.io.I := reset
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val sysclk: Clock = _outer.sysClkNode.out.head._1.clock
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val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
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_outer.sdc.addAsyncPath(Seq(powerOnReset))
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val ereset: Bool = _outer.chiplink.get() match {
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case Some(x: ChipLinkVC707PlacedOverlay) => !x.ereset_n
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case _ => false.B
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}
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_outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset)
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// reset setup
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val hReset = Wire(Reset())
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hReset := _outer.dutClock.in.head._1.reset
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val buildtopClock = _outer.dutClock.in.head._1.clock
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val buildtopReset = WireInit(hReset)
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val dutReset = hReset.asAsyncReset
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val success = false.B
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childClock := buildtopClock
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childReset := buildtopReset
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// harness binders are non-lazy
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_outer.topDesign match { case d: HasIOBinders =>
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ApplyHarnessBinders(this, d.lazySystem, d.portMap)
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}
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// check the top-level reference clock is equal to the default
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// non-exhaustive since you need all ChipTop clocks to equal the default
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require(getRefClockFreq == p(DefaultClockFrequencyKey))
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val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
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implicitHarnessClockBundle.clock := buildtopClock
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implicitHarnessClockBundle.reset := buildtopReset
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harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
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}
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