99 lines
3.8 KiB
Scala
99 lines
3.8 KiB
Scala
package chipyard.fpga.arty100t
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.diplomacy._
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import org.chipsalliance.cde.config.{Parameters}
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import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset}
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import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
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import sifive.fpgashells.shell.xilinx._
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import sifive.fpgashells.shell._
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import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
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import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
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import sifive.blocks.devices.uart._
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import chipyard.{ChipTop, CanHaveMasterTLMemPort, ExtTLMem}
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import chipyard.harness._
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import chipyard.iobinders.{HasIOBinders}
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class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences
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{
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def dp = designParameters
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val chiptop = LazyModule(p(BuildTop)(p))
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val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
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val harnessSysPLL = dp(PLLFactoryKey)
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val harnessSysPLLNode = harnessSysPLL()
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println(s"Arty100T FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
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val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
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val dutWrangler = LazyModule(new ResetWrangler())
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val dutGroup = ClockGroup()
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dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode
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harnessSysPLLNode := clockOverlay.overlayOutput.node
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val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
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val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
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val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
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val ddrInParams = chiptop match { case td: ChipTop =>
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td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
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lsys.memTLNode.edges.in(0)
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}
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}
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val ddrClient = TLClientNode(Seq(ddrInParams.master))
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val ddrBlockDuringReset = LazyModule(new TLBlockDuringReset(4))
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ddrOverlay.overlayOutput.ddr := ddrBlockDuringReset.node := ddrClient
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val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput()))
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val all_leds = ledOverlays.map(_.overlayOutput.led)
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val status_leds = all_leds.take(3)
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val other_leds = all_leds.drop(3)
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def buildtopClock = dutClock.in.head._1.clock
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def buildtopReset = dutClock.in.head._1.reset
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def success = { require(false, "Unused"); false.B }
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InModuleBody {
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clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
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val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock
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// Blink the status LEDs for sanity
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withClock(clk_100mhz) {
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val period = (BigInt(100) << 20) / status_leds.size
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val counter = RegInit(0.U(log2Ceil(period).W))
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val on = RegInit(0.U(log2Ceil(status_leds.size).W))
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status_leds.zipWithIndex.map { case (o,s) => o := on === s.U }
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counter := Mux(counter === (period-1).U, 0.U, counter + 1.U)
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when (counter === 0.U) {
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on := Mux(on === (status_leds.size-1).U, 0.U, on + 1.U)
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}
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}
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other_leds(0) := resetPin
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harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
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ddrOverlay.mig.module.clock := buildtopClock
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ddrOverlay.mig.module.reset := buildtopReset
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ddrBlockDuringReset.module.clock := buildtopClock
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ddrBlockDuringReset.module.reset := buildtopReset || !ddrOverlay.mig.module.io.port.init_calib_complete
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other_leds(6) := ddrOverlay.mig.module.io.port.init_calib_complete
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chiptop match { case d: HasIOBinders =>
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ApplyHarnessBinders(this, d.lazySystem, d.portMap)
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}
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val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
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implicitHarnessClockBundle.clock := buildtopClock
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implicitHarnessClockBundle.reset := buildtopReset
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harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
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}
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}
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