60 lines
2.2 KiB
Scala
60 lines
2.2 KiB
Scala
package example
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import chisel3._
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import freechips.rocketchip.config.{Config}
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// ---------------------
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// BOOM Configs
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// ---------------------
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class SmallBoomConfig extends Config(
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new WithTop ++ // use normal top
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new WithBootROM ++ // use testchipip bootrom
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive L2 cache
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new boom.common.WithSmallBooms ++ // 1-wide BOOM
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new boom.common.WithNBoomCores(1) ++ // single-core
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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class MediumBoomConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithMediumBooms ++ // 2-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class LargeBoomConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithLargeBooms ++ // 3-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class MegaBoomConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithMegaBooms ++ // 4-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class DualSmallBoomConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithSmallBooms ++
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new boom.common.WithNBoomCores(2) ++ // dual-core
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new freechips.rocketchip.system.BaseConfig)
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class SmallRV32UnifiedBoomConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithoutBoomFPU ++ // no floating point
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new boom.common.WithUnifiedMemIntIQs ++ // use unified mem+int issue queues
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new boom.common.WithSmallBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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