134 lines
6.0 KiB
Scala
134 lines
6.0 KiB
Scala
package chipyard
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import freechips.rocketchip.config.{Config}
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// This file is designed to accompany a live tutorial, with slides.
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// For each of 4 phases, participants will customize and build a
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// small demonstration config.
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// This file is designed to be used after running chipyard/scripts/tutorial-setup.sh,
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// which removes the SHA3 accelerator RTL, and provides participants
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// the experience of integrating external RTL.
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// This file was originally developed for the cancelled ASPLOS-2020
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// Chipyard tutorial. While the configs here work, the corresponding
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// slideware has not yet been created
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// NOTE: Configs should be read bottom-up, since they are applied bottom-up
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// Tutorial Phase 1: Configure the cores, caches
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class TutorialStarterConfig extends Config(
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// IOBinders specify how to connect to IOs in our TestHarness
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// These config fragments do not affect
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new chipyard.iobinders.WithUARTAdapter ++ // Connect a SimUART adapter to display UART on stdout
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new chipyard.iobinders.WithBlackBoxSimMem ++ // Connect simulated external memory
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new chipyard.iobinders.WithTieOffInterrupts ++ // Do not simulate external interrupts
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new chipyard.iobinders.WithTiedOffDebug ++ // Disconnect the debug module, since we use TSI for bring-up
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new chipyard.iobinders.WithSimSerial ++ // Connect external SimSerial widget to drive TSI
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// Config fragments below this line affect hardware generation
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// of the Top
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new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core
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new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM
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new chipyard.config.WithUART ++ // Add a UART
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// CUSTOMIZE THE CORE
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// Uncomment out one (or multiple) of the lines below, and choose
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// how many cores you want.
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// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores
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// new boom.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores
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// CUSTOMIZE the L2
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// Uncomment this line, and specify a size if you want to have a L2
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// new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks=1, nWays=4, capacityKB=128) ++
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// For simpler designs, we want to minimize IOs on
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// our Top. These config fragments remove unnecessary
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// ports
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
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// BaseConfig configures "bare" rocketchip system
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new freechips.rocketchip.system.BaseConfig
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)
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// Tutorial Phase 2: Integrate a TileLink or AXI4 MMIO device
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class TutorialMMIOConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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// Attach either a TileLink or AXI4 version of GCD
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// Uncomment one of the below lines
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// new chipyard.example.WithGCD(useAXI4=false) ++ // Use TileLink version
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// new chipyard.example.WithGCD(useAXI4=true) ++ // Use AXI4 version
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// For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig
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)
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// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator
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class TutorialSha3Config extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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// Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo
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// new sha3.WithSha3Accel ++
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// For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig
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)
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// Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator
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class TutorialSha3BlackBoxConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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// Uncomment these lines once SHA3 is integrated
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// new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl
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// new sha3.WithSha3Accel ++
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// For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig
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)
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