36 lines
1.6 KiB
ReStructuredText
36 lines
1.6 KiB
ReStructuredText
The RISC-V ISA Simulator (Spike)
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=================================
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Spike is the golden reference functional RISC-V ISA C++ sofware simulator.
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It provides full system emulation or proxied emulation with `HTIF/FESVR <https://github.com/riscv/riscv-isa-sim/tree/master/fesvr>`__.
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It serves as a starting point for running software on a RISC-V target.
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Here is a highlight of some of Spikes main features:
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* Multiple ISAs: RV32IMAFDQCV extensions
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* Multiple memory models: Weak Memory Ordering (WMO) and Total Store Ordering (TSO)
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* Privileged Spec: Machine, Supervisor, User modes (v1.11)
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* Debug Spec
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* Single-step debugging with support for viewing memory/register contents
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* Multiple CPU support
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* JTAG support
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* Highly extensible (add and test new instructions)
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In most cases, software development for a Chipyard target will begin with functional simulation using Spike
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(usually with the addition of custom Spike models for custom accelerator functions), and only later move on to
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full cycle-accurate simulation using software RTL simulators or FireSim.
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Spike comes pre-packaged in the RISC-V toolchain and is available on the path as ``spike``.
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More information can be found in the `Spike repository <https://github.com/riscv/riscv-isa-sim>`__.
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Spike-as-a-Tile
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-----------------
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Chipyard contains experimental support for simulating a Spike processor model with the uncore, similar to a virtual-platform.
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In this configuration, Spike is cache-coherent, and communicates with the uncore through a C++ TileLink private cache model.
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.. code-block:: shell
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make CONFIG=SpikeConfig run-binary BINARY=hello.riscv
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