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cf4e383805bc7b63cd85474e2befb7e0ca2d244c
chipyard
/
sims
/
vsim
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.gitignore
abejgonzalez
c364869563
default to .gitignoring all files in verisim/vsim | read verilator.mk
2019-03-12 14:39:15 -07:00
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!.gitignore
!Makefile
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