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cc0d33ee4dcb6cc2519df2571f52408c6f08578c
chipyard/sims/verisim
History
abejgonzalez cc0d33ee4d updated permissive naming | small bugfix for vcd/vpd dumping
2019-05-20 17:19:46 -07:00
..
.gitignore
default to .gitignoring all files in verisim/vsim | read verilator.mk
2019-03-12 14:39:15 -07:00
Makefile
updated permissive naming | small bugfix for vcd/vpd dumping
2019-05-20 17:19:46 -07:00
verilator.mk
Add verilator_install make target for CI purposes
2019-05-10 17:06:03 -07:00
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