90 lines
3.0 KiB
Scala
90 lines
3.0 KiB
Scala
package chipyard.config
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import scala.util.matching.Regex
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import chisel3._
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import chisel3.util.{log2Up}
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import org.chipsalliance.cde.config.{Config}
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import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey}
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import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}
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import freechips.rocketchip.stage.phases.TargetDirKey
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tile.{XLen}
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.spi._
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import testchipip._
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import chipyard.{ExtTLMem}
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// Set the bootrom to the Chipyard bootrom
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class WithBootROM extends Config((site, here, up) => {
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case BootROMLocated(x) => up(BootROMLocated(x), site)
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.map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img"))
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})
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// DOC include start: gpio config fragment
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class WithGPIO extends Config((site, here, up) => {
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case PeripheryGPIOKey => Seq(
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GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
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})
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// DOC include end: gpio config fragment
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class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {
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case PeripheryUARTKey => Seq(
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UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
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})
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class WithNoUART extends Config((site, here, up) => {
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case PeripheryUARTKey => Nil
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})
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class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => {
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case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
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})
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class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {
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// Note: the default size matches freedom with the addresses below
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case PeripherySPIFlashKey => Seq(
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SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size))
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})
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class WithDMIDTM extends Config((site, here, up) => {
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case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI))
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})
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class WithNoDebug extends Config((site, here, up) => {
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case DebugModuleKey => None
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})
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class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
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case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
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})
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class WithTLBackingMemory extends Config((site, here, up) => {
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case ExtMem => None // disable AXI backing memory
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case ExtTLMem => up(ExtMem, site) // enable TL backing memory
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})
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class WithSerialTLBackingMemory extends Config((site, here, up) => {
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case ExtMem => None
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case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(
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memParams = {
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val memPortParams = up(ExtMem, site).get
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require(memPortParams.nMemoryChannels == 1)
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memPortParams.master
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},
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isMemoryDevice = true
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)}
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})
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class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
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case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
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})
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class WithNoPLIC extends Config((site, here, up) => {
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case PLICKey => None
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})
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