65 lines
1.9 KiB
Scala
65 lines
1.9 KiB
Scala
package chipyard.fpga.vcu118.bringup
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import chisel3._
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import chisel3.experimental.{Analog, IO, BaseModule}
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import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
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import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
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import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
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import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
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import chipyard.{HasHarnessSignalReferences}
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import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
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/*** UART ***/
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class WithBringupUART extends ComposeHarnessBinder({
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(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
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th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
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require(ports.size == 2)
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vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last
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} }
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Nil
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}
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})
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/*** SPI ***/
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class WithBringupSPI extends ComposeHarnessBinder({
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(system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
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th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
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require(ports.size == 2)
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vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last
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} }
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Nil
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}
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})
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/*** I2C ***/
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class WithBringupI2C extends OverrideHarnessBinder({
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(system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
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th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
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require(ports.size == 1)
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vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head
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} }
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Nil
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}
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})
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/*** GPIO ***/
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class WithBringupGPIO extends OverrideHarnessBinder({
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(system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => {
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th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
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(vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
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bb_io.bundle <> dut_io
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}
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} }
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Nil
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}
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})
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