24 lines
720 B
Scala
24 lines
720 B
Scala
package chipyard.fpga.arty
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import chisel3._
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import chisel3.experimental.{IO}
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
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import chipyard.iobinders.{ComposeIOBinder, DebugResetPort, JTAGResetPort}
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class WithDebugResetPassthrough extends ComposeIOBinder({
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(system: HasPeripheryDebug) => {
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// Debug module reset
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val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
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io_ndreset := system.debug.get.ndreset
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// JTAG reset
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val sjtag = system.debug.get.systemjtag.get
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val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
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sjtag.reset := io_sjtag_reset
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(Seq(DebugResetPort(() => io_ndreset), JTAGResetPort(() => io_sjtag_reset)), Nil)
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}
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})
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