93 lines
3.7 KiB
Scala
93 lines
3.7 KiB
Scala
// See LICENSE for license details.
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package chipyard.fpga.nexysvideo
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.diplomacy._
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import org.chipsalliance.cde.config.{Parameters}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.subsystem.{SystemBusKey}
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import freechips.rocketchip.prci._
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import sifive.fpgashells.shell.xilinx._
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import sifive.fpgashells.shell._
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import sifive.fpgashells.clocks._
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import sifive.blocks.devices.uart._
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import chipyard._
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import chipyard.harness._
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import chipyard.iobinders.{HasIOBinders}
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class NexysVideoHarness(override implicit val p: Parameters) extends NexysVideoShell {
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def dp = designParameters
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val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
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val harnessSysPLL = dp(PLLFactoryKey)
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val harnessSysPLLNode = harnessSysPLL()
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val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
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val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
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println(s"NexysVideo FPGA Base Clock Freq: ${dutFreqMHz} MHz")
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val dutWrangler = LazyModule(new ResetWrangler())
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val dutGroup = ClockGroup()
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dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode
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harnessSysPLLNode := clockOverlay.overlayOutput.node
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val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
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val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
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// Optional DDR
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val ddrOverlay = if (p(NexysVideoShellDDR)) Some(dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRNexysVideoPlacedOverlay]) else None
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val ddrClient = if (p(NexysVideoShellDDR)) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
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name = "chip_ddr",
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sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
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)))))) else None
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val ddrBlockDuringReset = if (p(NexysVideoShellDDR)) Some(LazyModule(new TLBlockDuringReset(4))) else None
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if (p(NexysVideoShellDDR)) { ddrOverlay.get.overlayOutput.ddr := ddrBlockDuringReset.get.node := ddrClient.get }
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val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput()))
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val all_leds = ledOverlays.map(_.overlayOutput.led)
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val status_leds = all_leds.take(2)
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val other_leds = all_leds.drop(2)
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override lazy val module = new HarnessLikeImpl
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class HarnessLikeImpl extends Impl with HasHarnessInstantiators {
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all_leds.foreach(_ := DontCare)
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clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
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val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock
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// Blink the status LEDs for sanity
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withClockAndReset(clk_100mhz, dutClock.in.head._1.reset) {
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val period = (BigInt(100) << 20) / status_leds.size
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val counter = RegInit(0.U(log2Ceil(period).W))
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val on = RegInit(0.U(log2Ceil(status_leds.size).W))
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status_leds.zipWithIndex.map { case (o,s) => o := on === s.U }
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counter := Mux(counter === (period-1).U, 0.U, counter + 1.U)
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when (counter === 0.U) {
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on := Mux(on === (status_leds.size-1).U, 0.U, on + 1.U)
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}
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}
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other_leds(0) := resetPin
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harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
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def referenceClockFreqMHz = dutFreqMHz
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def referenceClock = dutClock.in.head._1.clock
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def referenceReset = dutClock.in.head._1.reset
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def success = { require(false, "Unused"); false.B }
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if (p(NexysVideoShellDDR)) {
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ddrOverlay.get.mig.module.clock := harnessBinderClock
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ddrOverlay.get.mig.module.reset := harnessBinderReset
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ddrBlockDuringReset.get.module.clock := harnessBinderClock
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ddrBlockDuringReset.get.module.reset := harnessBinderReset.asBool || !ddrOverlay.get.mig.module.io.port.init_calib_complete
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}
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instantiateChipTops()
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}
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}
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