124 lines
4.8 KiB
Scala
124 lines
4.8 KiB
Scala
//See LICENSE for license details.
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package firesim.firesim
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import java.io.File
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import scala.concurrent.{Future, Await, ExecutionContext}
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import scala.sys.process.{stringSeqToProcess, ProcessLogger}
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import scala.io.Source
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import org.scalatest.Suites
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite}
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import freechips.rocketchip.system.TestGeneration._
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import freechips.rocketchip.system.DefaultTestSuites._
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abstract class FireSimTestSuite(
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topModuleClass: String,
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targetConfigs: String,
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platformConfigs: String,
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N: Int = 8
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) extends firesim.TestSuiteCommon {
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import scala.concurrent.duration._
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import ExecutionContext.Implicits.global
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val topModuleProject = "firesim.firesim"
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val chipyardLongName = topModuleProject + "." + topModuleClass + "." + targetConfigs
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// From TestSuiteCommon
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val targetTuple = s"$topModuleClass-$targetConfigs-$platformConfigs"
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val commonMakeArgs = Seq(s"DESIGN=${topModuleClass}",
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s"TARGET_CONFIG=${targetConfigs}",
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s"PLATFORM_CONFIG=${platformConfigs}")
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override lazy val genDir = new File(firesimDir, s"generated-src/${chipyardLongName}")
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def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
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make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"),
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s"EMUL=${backend}")
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++ additionalArgs):_*)
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}
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def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
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compileMlSimulator(backend, debug)
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if (isCmdAvailable(backend)) {
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it should s"pass in ML simulation on ${backend}" in {
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assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0)
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}
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}
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}
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def runSuite(backend: String, debug: Boolean = false)(suite: RocketTestSuite) {
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// compile emulators
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behavior of s"${suite.makeTargetName} running on $backend"
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if (isCmdAvailable(backend)) {
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val postfix = suite match {
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case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv"
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case _ => ""
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}
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it should s"pass all tests in ${suite.makeTargetName}" in {
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val results = suite.names.toSeq sliding (N, N) map { t =>
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val subresults = t map (name =>
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Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
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Await result (Future sequence subresults, Duration.Inf)
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}
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results.flatten foreach { case (name, exitcode) =>
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assert(exitcode == 0, "Failed $name")
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}
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}
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} else {
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ignore should s"pass $backend"
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}
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}
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// Checks the collected trace log matches the behavior of a chisel printf
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def diffTracelog(verilatedLog: String) {
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behavior of "captured instruction trace"
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it should s"match the chisel printf in ${verilatedLog}" in {
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def getLines(file: File): Seq[String] = Source.fromFile(file).getLines.toList
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val printfPrefix = "TRACEPORT 0: "
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val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")).collect({
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case line if line.startsWith(printfPrefix) => line.stripPrefix(printfPrefix) })
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// Last bit indicates the core was under reset; reject those tokens
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// Tail to drop the first token which is initialized in the channel
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val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).tail.filter(line =>
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(line.last.toInt & 1) == 0)
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assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1,
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s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}")
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assert(verilatedOutput.nonEmpty)
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for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
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assert(vPrint == sPrint)
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}
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}
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}
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mkdirs
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behavior of s"Tuple: ${targetTuple}"
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elaborateAndCompile()
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runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
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runSuite("verilator")(benchmarks)
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}
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class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config")
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class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config")
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class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config")
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// Multiclock tests
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class RocketMulticlockF1Tests extends FireSimTestSuite(
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"FireSim",
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"FireSimMulticlockRocketConfig",
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"WithSynthAsserts_BaseF1Config")
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class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config")
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// This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
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class CITests extends Suites(
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new RocketF1Tests,
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new BoomF1Tests,
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new RocketNICF1Tests,
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new RocketMulticlockF1Tests)
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