54 lines
2.0 KiB
Scala
54 lines
2.0 KiB
Scala
package chipyard.fpga.vc707
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import chisel3._
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import chisel3.experimental.{IO, DataMirror}
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import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody}
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import freechips.rocketchip.subsystem.{BaseSubsystem}
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import freechips.rocketchip.util.{HeterogeneousBag}
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import freechips.rocketchip.tilelink.{TLBundle}
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import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp}
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import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice}
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp}
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import chipyard.{CanHaveMasterTLMemPort}
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import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder}
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class WithUARTIOPassthrough extends OverrideIOBinder({
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(system: HasPeripheryUARTModuleImp) => {
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val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") }
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(io_uart_pins_temp zip system.uart).map { case (io, sysio) =>
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io <> sysio
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}
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(io_uart_pins_temp, Nil)
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}
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})
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class WithSPIIOPassthrough extends OverrideLazyIOBinder({
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(system: HasPeripherySPI) => {
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// attach resource to 1st SPI
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ResourceBinding {
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Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
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}
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InModuleBody {
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system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => {
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val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") }
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(io_spi_pins_temp zip system.spi).map { case (io, sysio) =>
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io <> sysio
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}
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(io_spi_pins_temp, Nil)
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} }
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}
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}
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})
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class WithTLIOPassthrough extends OverrideIOBinder({
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(system: CanHaveMasterTLMemPort) => {
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val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
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io_tl_mem_pins_temp <> system.mem_tl
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(Seq(io_tl_mem_pins_temp), Nil)
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}
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})
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