Jerry Zhao adebd634b4 Fix Arty100T Verilog build (#1608) ...

* Bump rocket-chip
* Bump fpga-shells
* Add Arty100T Verilog build to CI
* Fix Arty100T harness disconnected LEDs

2023-09-27 13:03:37 +02:00

..

build-extra-tests.sh

Use conda + Update initial setup docs

2022-08-23 00:44:21 +00:00

check-commit.sh

remove firesim from commit-on-main check since we always manage it ourselves

2023-06-30 12:32:25 +00:00

clean-old-files.sh

Move Chipyard CI to Github Actions

2021-10-01 14:31:02 -07:00

defaults.sh

Fix Arty100T Verilog build (#1608)

2023-09-27 13:03:37 +02:00

install-conda.sh

Fix CI conda path + use most recent conda in CI

2023-07-12 00:21:26 +00:00

remote-do-rtl-build.sh

Remove init-fpga scripts and references, init-submodules now also inits-fpga

2023-05-07 16:03:27 -07:00

remote-run-firesim-scala-tests.sh

Disable Vivado tests

2023-07-11 14:39:54 -07:00

run-tests.sh

Merge remote-tracking branch 'origin/main' into tetheredsim

2023-06-13 15:32:08 -07:00