102 lines
3.5 KiB
Scala
102 lines
3.5 KiB
Scala
package mdf.macrolib
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import org.scalatest.flatspec.AnyFlatSpec
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import org.scalatest.matchers.should.Matchers
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class ConfReaderSpec extends AnyFlatSpec with Matchers {
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/** Generate a read port in accordance with RenameAnnotatedMemoryPorts. */
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def generateReadPort(num: Int, width: Int, depth: Int): MacroPort = {
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MacroPort(
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address = PolarizedPort(s"R${num}_addr", ActiveHigh),
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clock = Some(PolarizedPort(s"R${num}_clk", PositiveEdge)),
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output = Some(PolarizedPort(s"R${num}_data", ActiveHigh)),
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width = Some(width),
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depth = Some(depth)
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)
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}
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/** Generate a write port in accordance with RenameAnnotatedMemoryPorts. */
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def generateWritePort(num: Int, width: Int, depth: Int, maskGran: Option[Int] = None): MacroPort = {
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MacroPort(
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address = PolarizedPort(s"W${num}_addr", ActiveHigh),
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clock = Some(PolarizedPort(s"W${num}_clk", PositiveEdge)),
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input = Some(PolarizedPort(s"W${num}_data", ActiveHigh)),
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maskPort = if (maskGran.isDefined) Some(PolarizedPort(s"W${num}_mask", ActiveHigh)) else None,
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maskGran = maskGran,
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width = Some(184),
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depth = Some(128)
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)
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}
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"ConfReader" should "read a 1rw conf line" in {
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val confStr = "name Foo_Bar_mem123_ext depth 128 width 184 ports mrw mask_gran 23"
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ConfReader.readSingleLine(confStr) shouldBe SRAMMacro(
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name = "Foo_Bar_mem123_ext",
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width = 184,
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depth = 128,
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family = "1rw",
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ports = List(
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MacroPort(
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address = PolarizedPort("RW0_addr", ActiveHigh),
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clock = Some(PolarizedPort("RW0_clk", PositiveEdge)),
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writeEnable = Some(PolarizedPort("RW0_wmode", ActiveHigh)),
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output = Some(PolarizedPort("RW0_wdata", ActiveHigh)),
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input = Some(PolarizedPort("RW0_rdata", ActiveHigh)),
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maskPort = Some(PolarizedPort("RW0_wmask", ActiveHigh)),
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maskGran = Some(23),
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width = Some(184),
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depth = Some(128)
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)
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),
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extraPorts = List()
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)
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}
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"ConfReader" should "read a 1r1w conf line" in {
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val confStr = "name Foo_Bar_mem321_ext depth 128 width 184 ports read,mwrite mask_gran 23"
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ConfReader.readSingleLine(confStr) shouldBe SRAMMacro(
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name = "Foo_Bar_mem321_ext",
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width = 184,
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depth = 128,
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family = "1r1w",
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ports = List(
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generateReadPort(0, 184, 128),
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generateWritePort(0, 184, 128, Some(23))
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),
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extraPorts = List()
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)
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}
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"ConfReader" should "read a mixed 1r2w conf line" in {
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val confStr = "name Foo_Bar_mem321_ext depth 128 width 184 ports read,mwrite,write mask_gran 23"
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ConfReader.readSingleLine(confStr) shouldBe SRAMMacro(
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name = "Foo_Bar_mem321_ext",
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width = 184,
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depth = 128,
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family = "1r2w",
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ports = List(
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generateReadPort(0, 184, 128),
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generateWritePort(0, 184, 128, Some(23)),
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generateWritePort(1, 184, 128)
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),
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extraPorts = List()
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)
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}
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"ConfReader" should "read a 42r29w conf line" in {
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val confStr =
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"name Foo_Bar_mem321_ext depth 128 width 184 ports " + (Seq.fill(42)("read") ++ Seq.fill(29)("mwrite"))
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.mkString(",") + " mask_gran 23"
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ConfReader.readSingleLine(confStr) shouldBe SRAMMacro(
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name = "Foo_Bar_mem321_ext",
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width = 184,
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depth = 128,
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family = "42r29w",
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ports = ((0 to 41).map((num: Int) => generateReadPort(num, 184, 128))) ++
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((0 to 28).map((num: Int) => generateWritePort(num, 184, 128, Some(23)))),
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extraPorts = List()
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)
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}
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}
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