ac5235e5ed
* Refactor how Configs parameterize the Top and TestHarnesses * Bump sha3, testchipip, icenet, firesim
40 lines
2.3 KiB
ReStructuredText
40 lines
2.3 KiB
ReStructuredText
SiFive Generators
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==================
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Chipyard includes several open-source generators developed and maintained by `SiFive <https://www.sifive.com/>`__.
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These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``.
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Last-Level Cache Generator
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-----------------------------
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``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` mixin to your SoC configuration.
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To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
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Peripheral Devices
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-------------------
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``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
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These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
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To integrate one of these devices in your SoC, you will need to define a custom mixin with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following mixin to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers.
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.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala
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:language: scala
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:start-after: DOC include start: gpio mixin
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:end-before: DOC include end: gpio mixin
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Additionally, if the device requires top-level IOs, you will need to define a mixin to change the top-level configuration of your SoC.
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When adding a top-level IO, you should also be aware of whether it interacts with the test-harness.
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This example instantiates a top-level module with include GPIO ports (``TopWithGPIO``), and then ties-off the GPIO port inputs to 0 (``false.B``).
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Finally, you add the relevant config mixin to the SoC config. For example:
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.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
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:language: scala
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:start-after: DOC include start: GPIORocketConfig
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:end-before: DOC include end: GPIORocketConfig
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Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined mixins within the Chipyard example project. You may be able to use these config mixins directly, but you should be aware of their addresses within the SoC address map.
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