24 lines
924 B
Makefile
24 lines
924 B
Makefile
# See LICENSE for license details.
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base_dir=$(abspath ..)
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BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit
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FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx
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MODEL := E300ArtyDevKitFPGAChip
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PROJECT := sifive.freedom.everywhere.e300artydevkit
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export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
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export CONFIG := E300ArtyDevKitConfig
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export BOARD := arty
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export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip
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rocketchip_dir := $(base_dir)/generators/rocket-chip
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sifiveblocks_dir := $(base_dir)/generators/sifive-blocks
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VSRCS := \
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$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
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$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
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$(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \
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$(sifiveblocks_dir)/vsrc/SRLatch.v \
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$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
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include common.mk
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