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a6a50d41d00b94a7c03091a332a0bd23cdf74222
chipyard/vlsi/example-designs
History
Nayiri 42622919cd fixing macro paths for yosys with circt generated verilog [skip ci]
2023-12-14 18:02:32 -08:00
..
sky130-commercial.yml
Enable precommit | Format files
2023-08-28 14:56:55 -07:00
sky130-openroad-rockettile.yml
fixing macro paths for yosys with circt generated verilog [skip ci]
2023-12-14 18:02:32 -08:00
sky130-openroad.yml
Remove references to ENABLE_YOSYS
2023-12-13 10:07:14 -08:00
sky130-rocket.yml
renamed clock_clock to clock_uncore_clock
2023-06-30 15:04:38 -07:00
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