38 lines
1.3 KiB
Scala
38 lines
1.3 KiB
Scala
package chipyard.harness
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import chisel3._
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import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import org.chipsalliance.cde.config.{Field, Parameters}
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import freechips.rocketchip.util.{ResetCatchAndSync}
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import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
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import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
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import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
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import chipyard.{ChipTop}
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// -------------------------------
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// Chipyard Test Harness
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// -------------------------------
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class TestHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators {
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val io = IO(new Bundle {
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val success = Output(Bool())
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})
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val success = WireInit(false.B)
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io.success := success
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override val supportsMultiChip = true
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// By default, the chipyard makefile sets the TestHarness implicit clock to be 1GHz
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// This clock shouldn't be used by this TestHarness however, as most users
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// will use the AbsoluteFreqHarnessClockInstantiator, which generates clocks
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// in verilog blackboxes
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def referenceClockFreqMHz = 1000.0
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def referenceClock = clock
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def referenceReset = reset
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val lazyDuts = instantiateChipTops()
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}
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