Files
chipyard/fpga/src/main/scala/arty/Configs.scala
2020-11-05 15:04:44 -08:00

51 lines
1.9 KiB
Scala

// See LICENSE for license details.
package chipyard.fpga.arty
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
import freechips.rocketchip.system._
import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import chipyard.{BuildSystem}
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(
UARTParams(address = 0x10013000))
case DTSTimebase => BigInt(32768)
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2,
idcodePartNum = 0x000,
idcodeManufId = 0x489,
debugIdleCycles = 5)
})
class TinyRocketArtyConfig extends Config(
new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++
new WithArtyResetHarnessBinder ++
new chipyard.iobinders.WithDebugIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
new WithResetPassthrough ++
new WithDefaultPeripherals ++
new chipyard.config.WithNoSubsystemDrivenClocks ++
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.With1TinyCore ++
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
new freechips.rocketchip.subsystem.WithJtagDTM ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)