43 lines
1.4 KiB
Scala
43 lines
1.4 KiB
Scala
// See LICENSE for license details.
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package barstools.tapeout.transforms
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import firrtl._
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import firrtl.ir._
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import firrtl.passes.Pass
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// This doesn't rename ExtModules under the assumption that they're some
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// Verilog black box and therefore can't be renamed. Since the point is to
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// allow FIRRTL to be linked together using "cat" and ExtModules don't get
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// emitted, this should be safe.
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class RenameModulesAndInstancesPass(rename: (String) => String) extends Pass {
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def renameInstances(body: Statement): Statement = {
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body match {
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case m: DefInstance => new DefInstance(m.info, m.name, rename(m.module))
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case m: WDefInstance => new WDefInstance(m.info, m.name, rename(m.module), m.tpe)
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case b: Block => new Block( b.stmts map { s => renameInstances(s) } )
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case s: Statement => s
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}
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}
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def run(c: Circuit): Circuit = {
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val modulesx = c.modules.map {
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case m: ExtModule => m
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case m: Module => new Module(m.info, rename(m.name), m.ports, renameInstances(m.body))
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}
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Circuit(c.info, modulesx, c.main)
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}
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}
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class RenameModulesAndInstances(rename: (String) => String) extends Transform with SeqTransformBased {
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def inputForm = LowForm
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def outputForm = LowForm
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def transforms = Seq(new RenameModulesAndInstancesPass(rename))
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def execute(state: CircuitState): CircuitState = {
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val ret = runTransforms(state)
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CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
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}
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}
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