96939c9ab6
They no longer compile with the latest Chisel/FIRRTL, and may not be supported. However, future work will need them, so this keeps the files around but are ignored by sbt.
63 lines
2.5 KiB
Scala
63 lines
2.5 KiB
Scala
// See LICENSE for license details.
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package barstools.tapeout.transforms.pads
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import firrtl._
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import firrtl.annotations._
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import firrtl.passes._
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import firrtl.ir._
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import barstools.tapeout.transforms._
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import scala.collection.mutable
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// Main Add IO Pad transform operates on low Firrtl
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class AddIOPadsTransform extends Transform with SeqTransformBased {
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override def inputForm: CircuitForm = LowForm
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override def outputForm: CircuitForm = LowForm
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val transformList = new mutable.ArrayBuffer[Transform]
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def transforms: Seq[Transform] = transformList
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override def execute(state: CircuitState): CircuitState = {
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val collectedAnnos = HasPadAnnotation(getMyAnnotations(state))
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collectedAnnos match {
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// Transform not used
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case None => state
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case Some(x) =>
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val techLoc = (new TechnologyLocation).get(state)
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// Get foundry pad templates from yaml
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val foundryPads = FoundryPadsYaml.parse(techLoc)
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val portPads = AnnotatePortPads(state.circuit, x.topModName, foundryPads, x.componentAnnos,
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HasPadAnnotation.getSide(x.defaultPadSide))
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val supplyPads = AnnotateSupplyPads(foundryPads, x.supplyAnnos)
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val (circuitWithBBs, bbAnnotations) = CreatePadBBs(state.circuit, portPads, supplyPads)
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val namespace = Namespace(state.circuit)
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val padFrameName = namespace newName s"${x.topModName}_PadFrame"
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val topInternalName = namespace newName s"${x.topModName}_Internal"
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val targetDir = barstools.tapeout.transforms.GetTargetDir(state)
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PadPlacementFile.generate(techLoc, targetDir, padFrameName, portPads, supplyPads)
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transformList ++= Seq(
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Legalize,
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ResolveGenders,
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// Types really need to be known...
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InferTypes,
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new AddPadFrame(x.topModName, padFrameName, topInternalName, portPads, supplyPads),
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RemoveEmpty,
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CheckInitialization,
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InferTypes,
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Uniquify,
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ResolveKinds,
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ResolveGenders
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)
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// Expects BlackBox helper to be run after to inline pad Verilog!
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val ret = runTransforms(state)
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val currentAnnos = ret.annotations.getOrElse(AnnotationMap(Seq.empty)).annotations
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val newAnnoMap = AnnotationMap(currentAnnos ++ bbAnnotations)
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val newState = CircuitState(ret.circuit, outputForm, Some(newAnnoMap), ret.renames)
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// TODO: *.f file is overwritten on subsequent executions, but it doesn't seem to be used anywhere?
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(new firrtl.transforms.BlackBoxSourceHelper).execute(newState)
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}
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}
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} |