Jerry Zhao 9588d7536c Have PRCI control registers be clocked by the bus they hang off of (#1109) ...

This was technically correct before if the CBUS clock was the implicit clock. but this change makes it correct when that is not the case

2022-02-08 11:03:55 -08:00

..

boom @ e1a70afed7

bump boom along same PR

2020-12-23 15:00:57 +00:00

chipyard/src

Have PRCI control registers be clocked by the bus they hang off of (#1109)

2022-02-08 11:03:55 -08:00

cva6 @ 4717390310

Fix whitespace

2021-06-28 20:42:38 -07:00

fft-generator @ b9f1c085af

Bump fft-generator commit

2022-01-24 16:14:00 -08:00

firechip/src

[firechip] Properly string interpolate exit failure in ScalaTestSuite (#1095)

2022-01-21 08:48:27 -08:00

gemmini @ 72461235cc

bump gemmini to v0.6.2

2022-01-17 09:47:15 -08:00

hwacha @ 62c01f5a88

Bump hwacha for ucb-bar/hwacha#24

2020-12-18 20:52:00 +00:00

ibex @ bdf41a0548

Address PR comments for Ibex

2021-11-21 19:27:38 -08:00

icenet @ 084ca50706

Bump icenet

2020-12-10 06:34:39 +00:00

nvdla @ b2b78c9f89

NVDLA Integration + Cleanup Ariane Preprocessing (#505)

2020-05-16 12:22:30 -07:00

riscv-sodor @ 50a4925d5a

Bump sodor for val io fix

2022-01-19 14:15:43 -08:00

rocket-chip @ a7b016e46e

Start RC bump

2020-12-18 18:00:21 +00:00

sha3 @ 63eda8268c

Bump the sha3 repo to get software updates for the tutorial

2021-06-11 19:38:10 -04:00

sifive-blocks @ 545a396f34

Bump sifive-blocks

2021-01-08 10:56:30 -08:00

sifive-cache @ e3a3000cc1

bump sifive-cache for merged sifive/block-inclusivecache-sifive#15

2020-12-21 18:15:49 +00:00

testchipip @ 5917176c91

Point to testchipip bootrom file changes

2021-11-21 19:27:38 -08:00

tracegen

Add bypass to ignore simulator dependency

2021-10-18 10:33:49 -07:00