77 lines
2.6 KiB
Scala
77 lines
2.6 KiB
Scala
package tracegen
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import chisel3._
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import chisel3.util.log2Ceil
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import freechips.rocketchip.config.{Config, Parameters}
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import freechips.rocketchip.groundtest.{TraceGenParams}
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import freechips.rocketchip.subsystem.{ExtMem, SystemBusKey, WithInclusiveCache, InclusiveCacheKey}
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import freechips.rocketchip.system.BaseConfig
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import freechips.rocketchip.rocket.DCacheParams
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import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
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import scala.math.{max, min}
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class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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extends Config((site, here, up) => {
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case TraceGenKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val nSets = dcp.nSets
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val nWays = dcp.nWays
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val blockOffset = site(SystemBusKey).blockOffset
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val nBeats = min(2, site(SystemBusKey).blockBeats)
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val beatBytes = site(SystemBusKey).beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).get.master.base,
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numGens = params.size)
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}
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case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
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})
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class TraceGenConfig extends Config(
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new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
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new BaseConfig)
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class NonBlockingTraceGenConfig extends Config(
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new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
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new BaseConfig)
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class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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extends Config((site, here, up) => {
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case TraceGenKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val sbp = site(SystemBusKey)
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val l2p = site(InclusiveCacheKey)
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val nSets = max(l2p.sets, dcp.nSets)
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val nWays = max(l2p.ways, dcp.nWays)
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val blockOffset = sbp.blockOffset
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val nBeats = min(2, sbp.blockBeats)
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val beatBytes = sbp.beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).get.master.base,
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numGens = params.size)
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}
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case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
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})
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class NonBlockingTraceGenL2Config extends Config(
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new WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
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new WithInclusiveCache ++
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new BaseConfig)
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