57ee757016
Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link. This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder would effectively implement a similar system as what would go on the bringup platform. Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop are supported, we can remove all this old Harness-level stuff to reduce duplication
72 lines
2.4 KiB
Scala
72 lines
2.4 KiB
Scala
package chipyard.example
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import chisel3._
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import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
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import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
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import org.chipsalliance.cde.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters}
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import freechips.rocketchip.util.{PlusArg}
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import freechips.rocketchip.subsystem.{CacheBlockBytes}
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import freechips.rocketchip.devices.debug.{SimJTAG}
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import freechips.rocketchip.jtag.{JTAGIO}
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import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI}
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import chipyard.harness.{BuildTop}
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// A "flat" TestHarness that doesn't use IOBinders
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// use with caution.
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// This example is hard-coded to work only for FlatChipTop, and the ChipLikeRocketConfig
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class FlatTestHarness(implicit val p: Parameters) extends Module {
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val io = IO(new Bundle {
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val success = Output(Bool())
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})
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// This only works with FlatChipTop
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val lazyDut = LazyModule(new FlatChipTop).suggestName("chiptop")
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val dut = Module(lazyDut.module)
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// Clock
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val clock_source = Module(new ClockSourceAtFreqFromPlusArg("slow_clk_freq_mhz"))
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clock_source.io.power := true.B
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clock_source.io.gate := false.B
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dut.clock_pad.clock := clock_source.io.clk
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// Reset
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dut.reset_pad := reset.asAsyncReset
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// Custom boot
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dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1)
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// Serialized TL
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val sVal = p(SerialTLKey).get
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val serialTLManagerParams = sVal.serialTLManagerParams.get
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require(serialTLManagerParams.isMemoryDevice)
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withClockAndReset(clock, reset) {
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val serial_bits = dut.serial_tl_pad.bits
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if (DataMirror.directionOf(dut.serial_tl_pad.clock) == Direction.Input) {
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dut.serial_tl_pad.clock := clock
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}
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val harnessRAM = TSIHarness.connectRAM(
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lazyDut.system.serdesser.get,
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serial_bits,
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reset)
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io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset)
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}
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// JTAG
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val jtag_wire = Wire(new JTAGIO)
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jtag_wire.TDO.data := dut.jtag_pad.TDO
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jtag_wire.TDO.driven := true.B
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dut.jtag_pad.TCK := jtag_wire.TCK
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dut.jtag_pad.TMS := jtag_wire.TMS
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dut.jtag_pad.TDI := jtag_wire.TDI
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val dtm_success = WireInit(false.B)
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val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, clock, reset.asBool, ~(reset.asBool), dtm_success)
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// UART
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UARTAdapter.connect(Seq(dut.uart_pad))
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}
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