62 lines
2.6 KiB
Scala
62 lines
2.6 KiB
Scala
package chipyard.fpga.arty100t
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import chisel3._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.jtag.{JTAGIO}
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import freechips.rocketchip.subsystem.{PeripheryBusKey}
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import freechips.rocketchip.tilelink.{TLBundle}
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import freechips.rocketchip.util.{HeterogeneousBag}
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import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
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import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
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import sifive.blocks.devices.pinctrl.{BasePin}
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import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
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import chipyard._
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import chipyard.harness._
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import chipyard.iobinders.JTAGChipIO
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import testchipip._
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class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({
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(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
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implicit val p = chipyard.iobinders.GetSystemParameters(system)
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ports.map({ port =>
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val ath = th.asInstanceOf[Arty100THarness]
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val freq = p(PeripheryBusKey).dtsFrequency.get
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val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
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withClockAndReset(th.buildtopClock, th.buildtopReset) {
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val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
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val uart_to_serial = Module(new UARTToSerial(
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freq, UARTParams(0, initBaudRate=uartBaudRate)))
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val serial_width_adapter = Module(new SerialWidthAdapter(
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narrowW = 8, wideW = SerialAdapter.SERIAL_TSI_WIDTH))
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serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
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ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide)
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ath.io_uart_bb.bundle <> uart_to_serial.io.uart
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ath.other_leds(1) := uart_to_serial.io.dropped
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ath.other_leds(9) := ram.module.io.adapter_state(0)
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ath.other_leds(10) := ram.module.io.adapter_state(1)
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ath.other_leds(11) := ram.module.io.adapter_state(2)
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ath.other_leds(12) := ram.module.io.adapter_state(3)
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}
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})
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}
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})
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class WithArty100TDDRTL extends OverrideHarnessBinder({
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(system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
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require(ports.size == 1)
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val artyTh = th.asInstanceOf[Arty100THarness]
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val bundles = artyTh.ddrClient.out.map(_._1)
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val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
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bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
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ddrClientBundle <> ports.head
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}
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})
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