80 lines
3.6 KiB
Bash
Executable File
80 lines
3.6 KiB
Bash
Executable File
#!/bin/bash
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# make parallelism
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CI_MAKE_NPROC=4
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# chosen based on a 24c system shared with 1 other project
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REMOTE_MAKE_NPROC=4
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# verilator version
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VERILATOR_VERSION=v4.034
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# remote variables
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CURRENT_BRANCH=$(git branch --show-current)
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# CI_DIR is defined externally based on the GH repository secret BUILDDIR
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HOME=`pwd`
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REMOTE_PREFIX=$CI_DIR/${GITHUB_REPOSITORY#*/}-$CURRENT_BRANCH
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REMOTE_WORK_DIR=$GITHUB_WORKSPACE
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REMOTE_RISCV_DIR=$GITHUB_WORKSPACE/riscv-tools-install
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REMOTE_ESP_DIR=$GITHUB_WORKSPACE/esp-tools-install
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REMOTE_CHIPYARD_DIR=$GITHUB_WORKSPACE
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REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator
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REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim
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REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga
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REMOTE_JAVA_OPTS="-Xmx10G -Xss8M"
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# Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI
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REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
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REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$GITHUB_SHA-verilator-install
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# local variables (aka within the docker container)
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LOCAL_CHECKOUT_DIR=$HOME/project
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LOCAL_RISCV_DIR=$HOME/riscv-tools-install
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LOCAL_ESP_DIR=$HOME/esp-tools-install
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LOCAL_CHIPYARD_DIR=$HOME
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LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator
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LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
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# key value store to get the build groups
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declare -A grouping
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grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket"
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grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
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grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
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grouping["group-tracegen"]="tracegen tracegen-boom"
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grouping["group-other"]="icenet testchipip"
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grouping["group-fpga"]="arty vcu118"
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# key value store to get the build strings
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declare -A mapping
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mapping["chipyard-rocket"]=""
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mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
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mapping["chipyard-lbwif"]=" CONFIG=LBWIFRocketConfig"
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mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
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mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
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mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig"
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mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig"
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mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
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mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig"
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mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
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mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
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mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
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mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
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mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
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mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
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mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
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mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
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mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
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mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
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mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
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mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
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mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
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mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
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mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
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mapping["icenet"]="SUB_PROJECT=icenet"
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mapping["testchipip"]="SUB_PROJECT=testchipip"
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mapping["arty"]="SUB_PROJECT=arty verilog"
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mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
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