101 lines
4.1 KiB
Scala
101 lines
4.1 KiB
Scala
//******************************************************************************
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// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
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// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
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//------------------------------------------------------------------------------
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package chipyard
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import chisel3._
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import chisel3.internal.sourceinfo.{SourceInfo}
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import freechips.rocketchip.prci._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.amba.axi4._
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import boom.common.{BoomTile}
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import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey}
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trait CanHaveHTIF { this: BaseSubsystem =>
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// Advertise HTIF if system can communicate with fesvr
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if (this match {
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case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
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case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
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case _ => false
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}) {
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ResourceBinding {
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val htif = new Device {
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def describe(resources: ResourceBindings): Description = {
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val compat = resources("compat").map(_.value)
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Description("htif", Map(
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"compatible" -> compat))
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}
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}
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Resource(htif, "compat").bind(ResourceString("ucb,htif0"))
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}
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}
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}
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class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
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with HasTiles
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with CanHaveHTIF
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{
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def coreMonitorBundles = tiles.map {
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case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
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case b: BoomTile => b.module.core.coreMonitorBundle
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}.toList
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// No-tile configs have to be handled specially.
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if (tiles.size == 0) {
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// no PLIC, so sink interrupts to nowhere
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require(!p(PLICKey).isDefined)
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val intNexus = IntNexusNode(sourceFn = x => x.head, sinkFn = x => x.head)
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val intSink = IntSinkNode(IntSinkPortSimple())
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intSink := intNexus :=* ibus.toPLIC
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// Need to have at least 1 driver to the tile notification sinks
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tileHaltXbarNode := IntSourceNode(IntSourcePortSimple())
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tileWFIXbarNode := IntSourceNode(IntSourcePortSimple())
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tileCeaseXbarNode := IntSourceNode(IntSourcePortSimple())
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// Sink reset vectors to nowhere
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val resetVectorSink = BundleBridgeSink[UInt](Some(() => UInt(28.W)))
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resetVectorSink := tileResetVectorNode
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}
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// Relying on [[TLBusWrapperConnection]].driveClockFromMaster for
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// bus-couplings that are not asynchronous strips the bus name from the sink
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// ClockGroup. This makes it impossible to determine which clocks are driven
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// by which bus based on the member names, which is problematic when there is
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// a rational crossing between two buses. Instead, provide all bus clocks
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// directly from the asyncClockGroupsNode in the subsystem to ensure bus
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// names are always preserved in the top-level clock names.
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//
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// For example, using a RationalCrossing between the Sbus and Cbus, and
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// driveClockFromMaster = Some(true) results in all cbus-attached device and
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// bus clocks to be given names of the form "subsystem_sbus_[0-9]*".
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// Conversly, if an async crossing is used, they instead receive names of the
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// form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases.
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Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc =>
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tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode }
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}
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override lazy val module = new ChipyardSubsystemModuleImp(this)
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}
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class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
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with HasTilesModuleImp
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{
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// Generate C header with relevant information for Dromajo
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// This is included in the `dromajo_params.h` header file
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DromajoHelper.addArtefacts(InSubsystem)
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}
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