126 lines
5.4 KiB
Scala
126 lines
5.4 KiB
Scala
package barstools.tapeout.transforms
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import barstools.tapeout.transforms.stage._
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import firrtl._
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import firrtl.annotations._
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import firrtl.ir._
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import firrtl.options.{Dependency, InputAnnotationFileAnnotation, StageMain}
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import firrtl.passes.memlib.ReplSeqMemAnnotation
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import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage, OutputFileAnnotation, RunFirrtlTransformAnnotation}
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import firrtl.transforms.BlackBoxResourceFileNameAnno
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import logger.LazyLogging
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// Requires two phases, one to collect modules below synTop in the hierarchy
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// and a second to remove those modules to generate the test harness
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private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogging {
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val synTop: Option[String] = annotations.collectFirst { case SynTopAnnotation(s) => s }
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val topFir: Option[String] = annotations.collectFirst { case TopFirAnnotation(s) => s }
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val harnessFir: Option[String] = annotations.collectFirst { case HarnessFirAnnotation(s) => s }
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val topAnnoOut: Option[String] = annotations.collectFirst { case TopAnnoOutAnnotation(s) => s }
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val harnessAnnoOut: Option[String] = annotations.collectFirst { case HarnessAnnoOutAnnotation(s) => s }
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val harnessTop: Option[String] = annotations.collectFirst { case HarnessTopAnnotation(h) => h }
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val harnessConf: Option[String] = annotations.collectFirst { case HarnessConfAnnotation(h) => h }
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val harnessOutput: Option[String] = annotations.collectFirst { case HarnessOutputAnnotation(h) => h }
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val topDotfOut: Option[String] = annotations.collectFirst { case TopDotfOutAnnotation(h) => h }
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val harnessDotfOut: Option[String] = annotations.collectFirst { case HarnessDotfOutAnnotation(h) => h }
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val annoFiles: List[String] = annotations.flatMap {
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case InputAnnotationFileAnnotation(f) => Some(f)
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case _ => None
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}.toList
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lazy val rootCircuitTarget = CircuitTarget(harnessTop.get)
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val topAnnos = synTop.map(st => ReParentCircuitAnnotation(rootCircuitTarget.module(st))) ++
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topDotfOut.map(BlackBoxResourceFileNameAnno)
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// Dump firrtl and annotation files
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protected def dump(
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circuit: Circuit,
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annotations: AnnotationSeq,
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firFile: Option[String],
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annoFile: Option[String]
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): Unit = {
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firFile.foreach { firPath =>
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val outputFile = new java.io.PrintWriter(firPath)
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outputFile.write(circuit.serialize)
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outputFile.close()
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}
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annoFile.foreach { annoPath =>
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val outputFile = new java.io.PrintWriter(annoPath)
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outputFile.write(JsonProtocol.serialize(annotations.filter(_ match {
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case _: DeletedAnnotation => false
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case _: EmittedComponent => false
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case _: EmittedAnnotation[_] => false
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case _: FirrtlCircuitAnnotation => false
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case _ => true
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})))
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outputFile.close()
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}
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}
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// Top Generation
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def executeTop(): Seq[ExtModule] = {
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val annos = new FirrtlStage().execute(
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Array.empty,
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annotations ++ Seq(
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RunFirrtlTransformAnnotation(Dependency[ReParentCircuit]),
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RunFirrtlTransformAnnotation(Dependency[RemoveUnusedModules])
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) ++
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topAnnos
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)
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annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
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case Some(circuit) =>
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dump(circuit, annos, topFir, topAnnoOut)
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circuit.modules.collect { case e: ExtModule => e }
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case _ =>
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throw new Exception(s"executeTop failed while executing FIRRTL!\n")
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}
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}
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// Top and harness generation
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def executeTopAndHarness(): Unit = {
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// Execute top and get list of ExtModules to avoid collisions
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val topExtModules = executeTop()
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// order is determined by DependencyAPIMigration
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val harnessAnnos =
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harnessDotfOut.map(BlackBoxResourceFileNameAnno).toSeq ++
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harnessTop.map(ht => ModuleNameSuffixAnnotation(rootCircuitTarget, s"_in${ht}")) ++
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synTop.map(st => ConvertToExtModAnnotation(rootCircuitTarget.module(st))) ++
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Seq(
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LinkExtModulesAnnotation(topExtModules),
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RunFirrtlTransformAnnotation(Dependency[ConvertToExtMod]),
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RunFirrtlTransformAnnotation(Dependency[RemoveUnusedModules]),
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RunFirrtlTransformAnnotation(Dependency[AvoidExtModuleCollisions]),
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RunFirrtlTransformAnnotation(Dependency[AddSuffixToModuleNames])
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)
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// For harness run, change some firrtlOptions (below) for harness phase
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// customTransforms: setup harness transforms, add AvoidExtModuleCollisions
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// outputFileNameOverride: change to harnessOutput
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// conf file must change to harnessConf by mapping annotations
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val generatorAnnotations = annotations
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.filterNot(_.isInstanceOf[OutputFileAnnotation])
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.map {
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case ReplSeqMemAnnotation(i, _) => ReplSeqMemAnnotation(i, harnessConf.get)
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case HarnessOutputAnnotation(s) => OutputFileAnnotation(s)
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case anno => anno
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} ++ harnessAnnos
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val annos = new FirrtlStage().execute(Array.empty, generatorAnnotations)
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annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
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case Some(circuit) =>
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dump(circuit, annos, harnessFir, harnessAnnoOut)
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case _ =>
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throw new Exception(s"executeTop failed while executing FIRRTL!\n")
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}
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}
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}
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object GenerateTop extends StageMain(new TapeoutStage(doHarness = false))
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object GenerateTopAndHarness extends StageMain(new TapeoutStage(doHarness = true))
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