105 lines
3.8 KiB
Scala
105 lines
3.8 KiB
Scala
package chipyard.iobinders
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import chisel3._
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import chisel3.experimental.{Analog}
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import sifive.blocks.devices.uart.{UARTPortIO}
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import sifive.blocks.devices.spi.{SPIFlashParams, SPIPortIO}
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import sifive.blocks.devices.gpio.{GPIOPortIO}
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import testchipip.util.{ClockedIO}
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import testchipip.serdes.{TLSerdesser, SerialIO, SerialTLParams}
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import testchipip.spi.{SPIChipIO}
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import testchipip.cosim.{TraceOutputTop, SpikeCosimConfig}
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import testchipip.iceblk.{BlockDeviceIO, BlockDeviceConfig}
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import testchipip.tsi.{UARTTSIIO}
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import icenet.{NICIOvonly, NICConfig}
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import org.chipsalliance.cde.config.{Parameters}
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import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}
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import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, SlavePortParams}
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import freechips.rocketchip.devices.debug.{ClockedDMIIO}
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import freechips.rocketchip.util.{HeterogeneousBag}
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import freechips.rocketchip.tilelink.{TLBundle}
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trait Port[T <: Data] {
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val getIO: () => T
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// port.io should only be called in the TestHarness context
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lazy val io = getIO()
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}
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trait HasChipyardPorts {
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def ports: Seq[Port[_]]
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}
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// These case classes are generated by IOBinders, and interpreted by HarnessBinders
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case class GPIOPort (val getIO: () => Analog, val gpioId: Int, val pinId: Int)
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extends Port[Analog]
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case class GPIOPinsPort (val getIO: () => GPIOPortIO, val gpioId: Int)
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extends Port[GPIOPortIO]
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case class I2CPort (val getIO: () => sifive.blocks.devices.i2c.I2CPort)
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extends Port[sifive.blocks.devices.i2c.I2CPort]
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case class UARTPort (val getIO: () => UARTPortIO, val uartNo: Int, val freqMHz: Int)
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extends Port[UARTPortIO]
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case class SPIFlashPort (val getIO: () => SPIChipIO, val params: SPIFlashParams, val spiId: Int)
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extends Port[SPIChipIO]
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case class SPIPort (val getIO: () => SPIPortIO)
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extends Port[SPIPortIO]
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case class BlockDevicePort (val getIO: () => ClockedIO[BlockDeviceIO], val params: BlockDeviceConfig)
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extends Port[ClockedIO[BlockDeviceIO]]
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case class NICPort (val getIO: () => ClockedIO[NICIOvonly], val params: NICConfig)
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extends Port[ClockedIO[NICIOvonly]]
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case class AXI4MemPort (val getIO: () => ClockedIO[AXI4Bundle], val params: MemoryPortParams, val edge: AXI4EdgeParameters, val clockFreqMHz: Int)
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extends Port[ClockedIO[AXI4Bundle]]
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case class AXI4MMIOPort (val getIO: () => ClockedIO[AXI4Bundle], val params: MasterPortParams, val edge: AXI4EdgeParameters)
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extends Port[ClockedIO[AXI4Bundle]]
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case class AXI4InPort (val getIO: () => ClockedIO[AXI4Bundle], val params: SlavePortParams)
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extends Port[ClockedIO[AXI4Bundle]]
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case class ExtIntPort (val getIO: () => UInt)
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extends Port[UInt]
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case class DMIPort (val getIO: () => ClockedDMIIO)
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extends Port[ClockedDMIIO]
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case class JTAGPort (val getIO: () => JTAGChipIO)
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extends Port[JTAGChipIO]
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case class SerialTLPort (val getIO: () => ClockedIO[SerialIO], val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
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extends Port[ClockedIO[SerialIO]]
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case class UARTTSIPort (val getIO: () => UARTTSIIO)
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extends Port[UARTTSIIO]
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case class SuccessPort (val getIO: () => Bool)
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extends Port[Bool]
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case class TracePort (val getIO: () => TraceOutputTop, val cosimCfg: SpikeCosimConfig)
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extends Port[TraceOutputTop]
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case class CustomBootPort (val getIO: () => Bool)
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extends Port[Bool]
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case class ClockPort (val getIO: () => Clock, val freqMHz: Double)
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extends Port[Clock]
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case class ResetPort (val getIO: () => AsyncReset)
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extends Port[Reset]
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case class DebugResetPort (val getIO: () => Reset)
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extends Port[Reset]
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case class JTAGResetPort (val getIO: () => Reset)
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extends Port[Reset]
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case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle])
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extends Port[HeterogeneousBag[TLBundle]]
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