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chipyard
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70a292c86b4d08eb950b837a4c8f0a615f83f10e
chipyard
/
sims
/
verisim
History
abejgonzalez
4cca0ed57e
bump verilator version
2019-06-19 09:35:46 -07:00
..
.gitignore
default to .gitignoring all files in verisim/vsim | read verilator.mk
2019-03-12 14:39:15 -07:00
Makefile
updated permissive naming | small bugfix for vcd/vpd dumping
2019-05-20 17:19:46 -07:00
verilator.mk
bump verilator version
2019-06-19 09:35:46 -07:00