56 lines
1.8 KiB
Scala
56 lines
1.8 KiB
Scala
package chipyard.fpga.vcu118
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import chisel3._
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import chisel3.experimental.{Analog, IO}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
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import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource}
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import freechips.rocketchip.config.{Parameters}
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import chipyard.{BuildSystem}
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.i2c._
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trait HasVCU118PlatformIO {
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val io_uart: Seq[UARTPortIO]
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val io_spi: Seq[SPIPortIO]
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val io_i2c: Seq[I2CPort]
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}
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class VCU118Platform(override implicit val p: Parameters) extends LazyModule {
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val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
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override lazy val module = new VCU118PlatformModule(this)
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}
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class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer)
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with HasVCU118PlatformIO {
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val io_uart = _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp =>
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val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex.map { case (p, i) => IO(new UARTPortIO(p)).suggestName(s"uart_$i") }
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(io_uart_pins_temp zip sys.uart).map { case (io, sysio) =>
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io <> sysio
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}
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io_uart_pins_temp
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}
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val io_spi = _outer.lazySystem.module match { case sys: HasPeripherySPIModuleImp =>
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val io_spi_pins_temp = p(PeripherySPIKey).zipWithIndex.map { case (p, i) => IO(new SPIPortIO(p)).suggestName(s"spi_$i") }
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(io_spi_pins_temp zip sys.spi).map { case (io, sysio) =>
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io <> sysio
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}
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io_spi_pins_temp
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}
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val io_i2c = _outer.lazySystem.module match { case sys: HasPeripheryI2CModuleImp =>
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val io_i2c_pins_temp = p(PeripheryI2CKey).zipWithIndex.map { case (p, i) => IO(new I2CPort).suggestName(s"i2c_$i") }
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(io_i2c_pins_temp zip sys.i2c).map { case (io, sysio) =>
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io <> sysio
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}
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io_i2c_pins_temp
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}
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}
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