47 lines
1.5 KiB
Scala
47 lines
1.5 KiB
Scala
package tracegen
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import chisel3._
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import org.chipsalliance.cde.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
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import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar}
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import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
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import freechips.rocketchip.subsystem._
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import boom.lsu.BoomTraceGenTile
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class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
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with InstantiatesHierarchicalElements
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with HasTileNotificationSinks
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with HasTileInputConstants
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with HasHierarchicalElementsRootContext
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with HasHierarchicalElements
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with CanHaveMasterAXI4MemPort {
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def coreMonitorBundles = Nil
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val tileStatusNodes = totalTiles.values.toSeq.collect {
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case t: GroundTestTile => t.statusNode.makeSink()
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case t: BoomTraceGenTile => t.statusNode.makeSink()
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}
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lazy val fakeClockDomain = sbus.generateSynchronousDomain
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lazy val clintOpt = None
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lazy val debugOpt = None
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lazy val plicOpt = None
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lazy val clintDomainOpt = Some(fakeClockDomain)
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lazy val plicDomainOpt = Some(fakeClockDomain)
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override lazy val module = new TraceGenSystemModuleImp(this)
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}
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class TraceGenSystemModuleImp(outer: TraceGenSystem)
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extends BaseSubsystemModuleImp(outer)
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{
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val success = IO(Output(Bool()))
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val status = dontTouch(DebugCombiner(outer.tileStatusNodes.map(_.bundle)))
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success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR
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}
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