48 lines
2.6 KiB
Scala
48 lines
2.6 KiB
Scala
package chipyard
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import org.chipsalliance.cde.config.{Config}
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import freechips.rocketchip.diplomacy.{AddressSet}
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import freechips.rocketchip.subsystem.{SBUS}
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import testchipip.soc.{OBUS}
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// ------------------------------------------------
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// Configs demonstrating chip-to-chip communication
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// ------------------------------------------------
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// Simple design which exposes a second serial-tl port that can connect to another instance of itself
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class SymmetricChipletRocketConfig extends Config(
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new testchipip.soc.WithChipIdPin ++ // Add pin to identify chips
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new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims
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new testchipip.serdes.WithSerialTL(Seq(
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testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga
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client = Some(testchipip.serdes.SerialTLClientParams()), // bringup serial-tl acts only as a client
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phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // bringup serial-tl is sync'd to external clock
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),
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testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
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client = Some(testchipip.serdes.SerialTLClientParams()), // chip-to-chip serial-tl acts as a client
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manager = Some(testchipip.serdes.SerialTLManagerParams( // chip-to-chip serial-tl managers other chip's memory
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memParams = Seq(testchipip.serdes.ManagerRAMParams(
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address = 0,
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size = 1L << 32,
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)),
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slaveWhere = OBUS
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)),
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phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
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))
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) ++
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new testchipip.soc.WithOffchipBusClient(SBUS, // obus provides path to other chip's memory
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blockRange = Seq(AddressSet(0, (1L << 32) - 1)), // The lower 4GB is mapped to this chip
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replicationBase = Some(1L << 32) // The upper 4GB goes off-chip
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) ++
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new testchipip.soc.WithOffchipBus ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
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class MultiSimSymmetricChipletRocketConfig extends Config(
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new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
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new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=1) ++
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new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
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new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
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)
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